A wideband balun‐LNA employing symmetrical CCC technique and balanced outputs
Abstract The conventional active CG‐CS balun low‐noise amplifiers (LNAs) with asymmetric outputs exploit a relatively weak output balance, limited IIP2, and high power consumption. This study presents a wideband balun‐LNA with symmetrical outputs. The proposed LNA utilizes a symmetrical capacitive c...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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Hindawi-IET
2021-07-01
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| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cds2.12029 |
| _version_ | 1797422617252069376 |
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| author | Razieh Eskandari Afshin Ebrahimi Hasan Faraji Baghtash |
| author_facet | Razieh Eskandari Afshin Ebrahimi Hasan Faraji Baghtash |
| author_sort | Razieh Eskandari |
| collection | DOAJ |
| description | Abstract The conventional active CG‐CS balun low‐noise amplifiers (LNAs) with asymmetric outputs exploit a relatively weak output balance, limited IIP2, and high power consumption. This study presents a wideband balun‐LNA with symmetrical outputs. The proposed LNA utilizes a symmetrical capacitive cross‐coupled (CCC) technique between active balun and resistor loads to achieve wideband output balancing, thereby enhancing the gain and linearity performance. In addition, double noise reduction techniques are exploited to implement symmetrical outputs, reduce power consumption, and avoid noise figure (NF) degradation. First, the common‐source (CS) stage in parallel with the common‐gate (CG) amplifier nullifies the noise of the CG transistor. Second, an Aux amplifier in the CS stage reduces the noise of the CS transistor and avoids scaling up the CS transistor with respect to the CG transistor. The proposed LNA is implemented in 0.18 μm complementary metal‐oxide semiconductor technology, and its performance is evaluated through spectre post‐layout simulations. The proposed LNA exhibits a voltage gain of 25.4 dB and an NF of 3.2–3.8 dB over 3 GHz operating bandwidth ranging from 1 to 4 GHz. The IIP3 and IIP2 are achieved as ‐1.66 dBm and +28.97 dBm, respectively. The proposed structure consumes 5.5 mW from 1.5V power supply and occupies an active area of 0.29 mm2. |
| first_indexed | 2024-03-09T07:35:58Z |
| format | Article |
| id | doaj.art-1a985f6a92d14825970ea176c90bcb1c |
| institution | Directory Open Access Journal |
| issn | 1751-858X 1751-8598 |
| language | English |
| last_indexed | 2024-03-09T07:35:58Z |
| publishDate | 2021-07-01 |
| publisher | Hindawi-IET |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj.art-1a985f6a92d14825970ea176c90bcb1c2023-12-03T05:39:51ZengHindawi-IETIET Circuits, Devices and Systems1751-858X1751-85982021-07-0115433033910.1049/cds2.12029A wideband balun‐LNA employing symmetrical CCC technique and balanced outputsRazieh Eskandari0Afshin Ebrahimi1Hasan Faraji Baghtash2Faculty of Electrical Engineering Sahand University of Technology Sahand New Town Tabriz IranFaculty of Electrical Engineering Sahand University of Technology Sahand New Town Tabriz IranFaculty of Electrical Engineering Sahand University of Technology Sahand New Town Tabriz IranAbstract The conventional active CG‐CS balun low‐noise amplifiers (LNAs) with asymmetric outputs exploit a relatively weak output balance, limited IIP2, and high power consumption. This study presents a wideband balun‐LNA with symmetrical outputs. The proposed LNA utilizes a symmetrical capacitive cross‐coupled (CCC) technique between active balun and resistor loads to achieve wideband output balancing, thereby enhancing the gain and linearity performance. In addition, double noise reduction techniques are exploited to implement symmetrical outputs, reduce power consumption, and avoid noise figure (NF) degradation. First, the common‐source (CS) stage in parallel with the common‐gate (CG) amplifier nullifies the noise of the CG transistor. Second, an Aux amplifier in the CS stage reduces the noise of the CS transistor and avoids scaling up the CS transistor with respect to the CG transistor. The proposed LNA is implemented in 0.18 μm complementary metal‐oxide semiconductor technology, and its performance is evaluated through spectre post‐layout simulations. The proposed LNA exhibits a voltage gain of 25.4 dB and an NF of 3.2–3.8 dB over 3 GHz operating bandwidth ranging from 1 to 4 GHz. The IIP3 and IIP2 are achieved as ‐1.66 dBm and +28.97 dBm, respectively. The proposed structure consumes 5.5 mW from 1.5V power supply and occupies an active area of 0.29 mm2.https://doi.org/10.1049/cds2.12029balunsCMOS integrated circuitsfield effect MMIClow noise amplifiersmicrowave amplifierswideband amplifiers |
| spellingShingle | Razieh Eskandari Afshin Ebrahimi Hasan Faraji Baghtash A wideband balun‐LNA employing symmetrical CCC technique and balanced outputs IET Circuits, Devices and Systems baluns CMOS integrated circuits field effect MMIC low noise amplifiers microwave amplifiers wideband amplifiers |
| title | A wideband balun‐LNA employing symmetrical CCC technique and balanced outputs |
| title_full | A wideband balun‐LNA employing symmetrical CCC technique and balanced outputs |
| title_fullStr | A wideband balun‐LNA employing symmetrical CCC technique and balanced outputs |
| title_full_unstemmed | A wideband balun‐LNA employing symmetrical CCC technique and balanced outputs |
| title_short | A wideband balun‐LNA employing symmetrical CCC technique and balanced outputs |
| title_sort | wideband balun lna employing symmetrical ccc technique and balanced outputs |
| topic | baluns CMOS integrated circuits field effect MMIC low noise amplifiers microwave amplifiers wideband amplifiers |
| url | https://doi.org/10.1049/cds2.12029 |
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