Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like rai...

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Bibliographic Details
Main Authors: Maher Fakih, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Mikel Azkarate-Askasua, Peio Onaindia, Tomaso Poggi, Nera González Romero, Elena Quesada Gonzalez, Timmy Sundström, Salvador Peiró Frasquet, Patricia Balbastre, Tage Mohammadat, Johnny Öberg, Yosab Bebawy, Roman Obermaisser, Adele Maleki, Alina Lenz, Duncan Graham
Format: Article
Language:English
Published: MDPI AG 2019-03-01
Series:Journal of Low Power Electronics and Applications
Subjects:
time-triggered
NoC-based communication
low-power
mixed-criticality
power-efficient
Online Access:http://www.mdpi.com/2079-9268/9/1/12

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