PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC

PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC

Bibliographic Details
Main Authors:	Rahimunnisa K., Karthigaikumar P., Christy N., Kumar S., Jayakumar J.
Format:	Article
Language:	English
Published:	De Gruyter 2013-12-01
Series:	Open Computer Science
Subjects:	cryptography aes fpga asic parallel sub-pipelined throughput
Online Access:	https://doi.org/10.2478/s13537-013-0112-2

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