A New Floating and Tunable Capacitance Multiplier With Large Multiplication Factor
This paper presents a CMOS floating and tunable capacitance multiplier with a very large multiplication factor. The proposed design uses CCII and OTAs designed using MOSFETs biased in subthreshold region to provide low power consumption and high multiplication factor. TANNER TSPICE simulation tool i...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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IEEE
2019-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/8808856/ |
| _version_ | 1818323518961483776 |
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| author | Munir Ahmad Al-Absi Abdulaziz Ahmed Al-Khulaifi |
| author_facet | Munir Ahmad Al-Absi Abdulaziz Ahmed Al-Khulaifi |
| author_sort | Munir Ahmad Al-Absi |
| collection | DOAJ |
| description | This paper presents a CMOS floating and tunable capacitance multiplier with a very large multiplication factor. The proposed design uses CCII and OTAs designed using MOSFETs biased in subthreshold region to provide low power consumption and high multiplication factor. TANNER TSPICE simulation tool is used to confirm the functionality of the design in 0.18μm TSMC CMOS technology. The circuit is powered using ±0.75V DC supply voltage. Simulation results indicate that the maximum multiplication factor is 3600 and the maximum error is 8.6%. |
| first_indexed | 2024-12-13T11:13:58Z |
| format | Article |
| id | doaj.art-1b4518527803461591fdd865203daf6c |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-13T11:13:58Z |
| publishDate | 2019-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-1b4518527803461591fdd865203daf6c2022-12-21T23:48:40ZengIEEEIEEE Access2169-35362019-01-01712007612008110.1109/ACCESS.2019.29368008808856A New Floating and Tunable Capacitance Multiplier With Large Multiplication FactorMunir Ahmad Al-Absi0https://orcid.org/0000-0002-5489-958XAbdulaziz Ahmed Al-Khulaifi1Electrical Engineering Department, King Fahd University of Petroleum and Minerals, Dhahran, Saudi ArabiaElectrical Engineering Department, King Fahd University of Petroleum and Minerals, Dhahran, Saudi ArabiaThis paper presents a CMOS floating and tunable capacitance multiplier with a very large multiplication factor. The proposed design uses CCII and OTAs designed using MOSFETs biased in subthreshold region to provide low power consumption and high multiplication factor. TANNER TSPICE simulation tool is used to confirm the functionality of the design in 0.18μm TSMC CMOS technology. The circuit is powered using ±0.75V DC supply voltage. Simulation results indicate that the maximum multiplication factor is 3600 and the maximum error is 8.6%.https://ieeexplore.ieee.org/document/8808856/Impedance multiplierfiltersbiomedical circuitshigh multiplication factortunable |
| spellingShingle | Munir Ahmad Al-Absi Abdulaziz Ahmed Al-Khulaifi A New Floating and Tunable Capacitance Multiplier With Large Multiplication Factor IEEE Access Impedance multiplier filters biomedical circuits high multiplication factor tunable |
| title | A New Floating and Tunable Capacitance Multiplier With Large Multiplication Factor |
| title_full | A New Floating and Tunable Capacitance Multiplier With Large Multiplication Factor |
| title_fullStr | A New Floating and Tunable Capacitance Multiplier With Large Multiplication Factor |
| title_full_unstemmed | A New Floating and Tunable Capacitance Multiplier With Large Multiplication Factor |
| title_short | A New Floating and Tunable Capacitance Multiplier With Large Multiplication Factor |
| title_sort | new floating and tunable capacitance multiplier with large multiplication factor |
| topic | Impedance multiplier filters biomedical circuits high multiplication factor tunable |
| url | https://ieeexplore.ieee.org/document/8808856/ |
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