HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices
In this paper, we present a fast hybrid priority queue architecture intended for scheduling and prioritizing packets in a network data plane. Due to increasing traffic and tight requirements of high-speed networking devices, a high capacity priority queue, with constant latency and guaranteed perfor...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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IEEE
2019-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8842569/ |
| _version_ | 1818596526251835392 |
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| author | Imad Benacer Francois-Raymond Boyer Yvon Savaria |
| author_facet | Imad Benacer Francois-Raymond Boyer Yvon Savaria |
| author_sort | Imad Benacer |
| collection | DOAJ |
| description | In this paper, we present a fast hybrid priority queue architecture intended for scheduling and prioritizing packets in a network data plane. Due to increasing traffic and tight requirements of high-speed networking devices, a high capacity priority queue, with constant latency and guaranteed performance is needed. We aim at reducing latency to best support the upcoming 5G wireless standards. The proposed hybrid priority queuing system (HPQS) enables pipelined queue operations with almost constant time complexity in practice. The proposed architecture is implemented in C++, and is synthesized with the Vivado High-Level Synthesis (HLS) tool. Two configurations are proposed. The first one is intended for scheduling with a multi-queuing system for which implementation results of 64 up to 512 independent queues are reported. The second configuration is intended for large capacity priority queues, that are placed and routed on a ZC706 board and a XCVU440-FLGB2377-3-E Xilinx FPGA supporting a total capacity of 1/2 million packet tags. The reported results are compared across a range of priority queue depths and performance metrics with existing approaches. The proposed HPQS supports links operating at 40 Gb/s. |
| first_indexed | 2024-12-16T11:33:18Z |
| format | Article |
| id | doaj.art-1c100f5346d04baa8b1a3f42e17e4171 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-16T11:33:18Z |
| publishDate | 2019-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-1c100f5346d04baa8b1a3f42e17e41712022-12-21T22:33:10ZengIEEEIEEE Access2169-35362019-01-01713067213068410.1109/ACCESS.2019.29391548842569HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking DevicesImad Benacer0https://orcid.org/0000-0001-9608-2474Francois-Raymond Boyer1Yvon Savaria2Department of Computer and Software Engineering, Polytechnique Montréal, Montréal, QC, CanadaDepartment of Computer and Software Engineering, Polytechnique Montréal, Montréal, QC, CanadaDepartment of Electrical Engineering, Polytechnique Montréal, Montréal, QC, CanadaIn this paper, we present a fast hybrid priority queue architecture intended for scheduling and prioritizing packets in a network data plane. Due to increasing traffic and tight requirements of high-speed networking devices, a high capacity priority queue, with constant latency and guaranteed performance is needed. We aim at reducing latency to best support the upcoming 5G wireless standards. The proposed hybrid priority queuing system (HPQS) enables pipelined queue operations with almost constant time complexity in practice. The proposed architecture is implemented in C++, and is synthesized with the Vivado High-Level Synthesis (HLS) tool. Two configurations are proposed. The first one is intended for scheduling with a multi-queuing system for which implementation results of 64 up to 512 independent queues are reported. The second configuration is intended for large capacity priority queues, that are placed and routed on a ZC706 board and a XCVU440-FLGB2377-3-E Xilinx FPGA supporting a total capacity of 1/2 million packet tags. The reported results are compared across a range of priority queue depths and performance metrics with existing approaches. The proposed HPQS supports links operating at 40 Gb/s.https://ieeexplore.ieee.org/document/8842569/Priority queuenetworking deviceshigh-level synthesisfield-programmable gate array (FPGA) |
| spellingShingle | Imad Benacer Francois-Raymond Boyer Yvon Savaria HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices IEEE Access Priority queue networking devices high-level synthesis field-programmable gate array (FPGA) |
| title | HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices |
| title_full | HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices |
| title_fullStr | HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices |
| title_full_unstemmed | HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices |
| title_short | HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices |
| title_sort | hpqs a fast high capacity hybrid priority queuing system for high speed networking devices |
| topic | Priority queue networking devices high-level synthesis field-programmable gate array (FPGA) |
| url | https://ieeexplore.ieee.org/document/8842569/ |
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