Hardware-Aware Design for Edge Intelligence
With the rapid growth of the number of devices connected to the Internet, there is a trend to move intelligent processing of the generated data with deep neural networks (DNNs) from cloud servers to the network edge. Performing inference and training of DNNs in edge hardware is motivated by latency...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2021-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9311412/ |
| _version_ | 1819120568640733184 |
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| author | Warren J. Gross Brett H. Meyer Arash Ardakani |
| author_facet | Warren J. Gross Brett H. Meyer Arash Ardakani |
| author_sort | Warren J. Gross |
| collection | DOAJ |
| description | With the rapid growth of the number of devices connected to the Internet, there is a trend to move intelligent processing of the generated data with deep neural networks (DNNs) from cloud servers to the network edge. Performing inference and training of DNNs in edge hardware is motivated by latency constraints, security and privacy concerns, and restricted network bandwidth. However, implementation of DNNs is challenging in resource-constrained edge devices. This article surveys recent advances in the efficient processing of DNNs, highlighting present research trends and future challenges. Specifically, we start by reviewing optimization methods for hardware-aware deployment of DNNs. We then present some case studies of promising new directions towards low-complexity on-chip training. Finally, we discuss future challenges and their potential solutions for efficient deployment of DNNs at the edge. |
| first_indexed | 2024-12-22T06:22:44Z |
| format | Article |
| id | doaj.art-1c4119090f8c4efc864e1044750614b6 |
| institution | Directory Open Access Journal |
| issn | 2644-1225 |
| language | English |
| last_indexed | 2024-12-22T06:22:44Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj.art-1c4119090f8c4efc864e1044750614b62022-12-21T18:35:54ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252021-01-01211312710.1109/OJCAS.2020.30474189311412Hardware-Aware Design for Edge IntelligenceWarren J. Gross0https://orcid.org/0000-0002-6226-6037Brett H. Meyer1https://orcid.org/0000-0002-6650-3298Arash Ardakani2https://orcid.org/0000-0003-3274-2394Department of Electrical and Computer Engineering, McGill University, Montreal, QC, CanadaDepartment of Electrical and Computer Engineering, McGill University, Montreal, QC, CanadaDepartment of Electrical and Computer Engineering, McGill University, Montreal, QC, CanadaWith the rapid growth of the number of devices connected to the Internet, there is a trend to move intelligent processing of the generated data with deep neural networks (DNNs) from cloud servers to the network edge. Performing inference and training of DNNs in edge hardware is motivated by latency constraints, security and privacy concerns, and restricted network bandwidth. However, implementation of DNNs is challenging in resource-constrained edge devices. This article surveys recent advances in the efficient processing of DNNs, highlighting present research trends and future challenges. Specifically, we start by reviewing optimization methods for hardware-aware deployment of DNNs. We then present some case studies of promising new directions towards low-complexity on-chip training. Finally, we discuss future challenges and their potential solutions for efficient deployment of DNNs at the edge.https://ieeexplore.ieee.org/document/9311412/Artificial intelligencedeep neural networkshardware and systemsneural architecture searchquantization and pruningstochastic computing |
| spellingShingle | Warren J. Gross Brett H. Meyer Arash Ardakani Hardware-Aware Design for Edge Intelligence IEEE Open Journal of Circuits and Systems Artificial intelligence deep neural networks hardware and systems neural architecture search quantization and pruning stochastic computing |
| title | Hardware-Aware Design for Edge Intelligence |
| title_full | Hardware-Aware Design for Edge Intelligence |
| title_fullStr | Hardware-Aware Design for Edge Intelligence |
| title_full_unstemmed | Hardware-Aware Design for Edge Intelligence |
| title_short | Hardware-Aware Design for Edge Intelligence |
| title_sort | hardware aware design for edge intelligence |
| topic | Artificial intelligence deep neural networks hardware and systems neural architecture search quantization and pruning stochastic computing |
| url | https://ieeexplore.ieee.org/document/9311412/ |
| work_keys_str_mv | AT warrenjgross hardwareawaredesignforedgeintelligence AT bretthmeyer hardwareawaredesignforedgeintelligence AT arashardakani hardwareawaredesignforedgeintelligence |