Improved dual sided doped memristor: modelling and applications
Memristor as a novel and emerging electronic device having vast range of applications suffer from poor frequency response and saturation length. In this paper, the authors present a novel and an innovative device structure for the memristor with two active layers and its non-linear ionic drift model...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2014-05-01
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| Series: | The Journal of Engineering |
| Subjects: | |
| Online Access: | http://digital-library.theiet.org/content/journals/10.1049/joe.2013.0265 |
| _version_ | 1818959936350060544 |
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| author | Anup Shrivastava Muhammad Khalid Komal Singh Jawar Singh |
| author_facet | Anup Shrivastava Muhammad Khalid Komal Singh Jawar Singh |
| author_sort | Anup Shrivastava |
| collection | DOAJ |
| description | Memristor as a novel and emerging electronic device having vast range of applications suffer from poor frequency response and saturation length. In this paper, the authors present a novel and an innovative device structure for the memristor with two active layers and its non-linear ionic drift model for an improved frequency response and saturation length. The authors investigated and compared the I–V characteristics for the proposed model with the conventional memristors and found better results in each case (different window functions) for the proposed dual sided doped memristor. For circuit level simulation, they developed a SPICE model of the proposed memristor and designed some logic gates based on hybrid complementary metal oxide semiconductor memristive logic (memristor ratioed logic). The proposed memristor yields improved results in terms of noise margin, delay time and dynamic hazards than that of the conventional memristors (single active layer memristors). |
| first_indexed | 2024-12-20T11:49:33Z |
| format | Article |
| id | doaj.art-1edc373ff4674fa2b5a98b41ef0a7cc3 |
| institution | Directory Open Access Journal |
| issn | 2051-3305 |
| language | English |
| last_indexed | 2024-12-20T11:49:33Z |
| publishDate | 2014-05-01 |
| publisher | Wiley |
| record_format | Article |
| series | The Journal of Engineering |
| spelling | doaj.art-1edc373ff4674fa2b5a98b41ef0a7cc32022-12-21T19:41:49ZengWileyThe Journal of Engineering2051-33052014-05-0110.1049/joe.2013.0265JOE.2013.0265Improved dual sided doped memristor: modelling and applicationsAnup Shrivastava0Muhammad Khalid1Komal Singh2Jawar Singh3Indian Institute of Information TechnologyIndian Institute of Information TechnologyIndian Institute of Information TechnologyIndian Institute of Information TechnologyMemristor as a novel and emerging electronic device having vast range of applications suffer from poor frequency response and saturation length. In this paper, the authors present a novel and an innovative device structure for the memristor with two active layers and its non-linear ionic drift model for an improved frequency response and saturation length. The authors investigated and compared the I–V characteristics for the proposed model with the conventional memristors and found better results in each case (different window functions) for the proposed dual sided doped memristor. For circuit level simulation, they developed a SPICE model of the proposed memristor and designed some logic gates based on hybrid complementary metal oxide semiconductor memristive logic (memristor ratioed logic). The proposed memristor yields improved results in terms of noise margin, delay time and dynamic hazards than that of the conventional memristors (single active layer memristors).http://digital-library.theiet.org/content/journals/10.1049/joe.2013.0265memristorsfrequency responsesemiconductor device modelslogic gatesdual sided doped memristorelectronic devicefrequency responsesaturation lengthdevice structureactive layersnonlinear ionic drift modelI–V characteristicscircuit level simulationSPICE modellogic gateshybrid complementary metal oxide semiconductor memristive logicmemristor ratioed logicnoise margindelay timedynamic hazardssingle active layer memristors |
| spellingShingle | Anup Shrivastava Muhammad Khalid Komal Singh Jawar Singh Improved dual sided doped memristor: modelling and applications The Journal of Engineering memristors frequency response semiconductor device models logic gates dual sided doped memristor electronic device frequency response saturation length device structure active layers nonlinear ionic drift model I–V characteristics circuit level simulation SPICE model logic gates hybrid complementary metal oxide semiconductor memristive logic memristor ratioed logic noise margin delay time dynamic hazards single active layer memristors |
| title | Improved dual sided doped memristor: modelling and applications |
| title_full | Improved dual sided doped memristor: modelling and applications |
| title_fullStr | Improved dual sided doped memristor: modelling and applications |
| title_full_unstemmed | Improved dual sided doped memristor: modelling and applications |
| title_short | Improved dual sided doped memristor: modelling and applications |
| title_sort | improved dual sided doped memristor modelling and applications |
| topic | memristors frequency response semiconductor device models logic gates dual sided doped memristor electronic device frequency response saturation length device structure active layers nonlinear ionic drift model I–V characteristics circuit level simulation SPICE model logic gates hybrid complementary metal oxide semiconductor memristive logic memristor ratioed logic noise margin delay time dynamic hazards single active layer memristors |
| url | http://digital-library.theiet.org/content/journals/10.1049/joe.2013.0265 |
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