| Summary: | In this article, we propose a nontraditional design of dynamic logic circuits using fully-depleted silicon-on-insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\text {t}}$ </tex-math></inline-formula>) to be adjustable (i.e., low-<inline-formula> <tex-math notation="LaTeX">$V_{\text {t}}$ </tex-math></inline-formula> and high-<inline-formula> <tex-math notation="LaTeX">$V_{\text {t}}$ </tex-math></inline-formula> states) by using the back gate (BG) bias. Our design utilizes the front gate (FG) and BG of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like a half-adder and full-adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14 nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product (PDP) of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge-sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates.
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