Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing
In this article, we propose a nontraditional design of dynamic logic circuits using fully-depleted silicon-on-insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\text {t}}$ </tex-math></inline-formula>) to...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10106142/ |
| _version_ | 1797808457548562432 |
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| author | Shubham Kumar Swetaki Chatterjee Chetan Kumar Dabhi Yogesh Singh Chauhan Hussam Amrouch |
| author_facet | Shubham Kumar Swetaki Chatterjee Chetan Kumar Dabhi Yogesh Singh Chauhan Hussam Amrouch |
| author_sort | Shubham Kumar |
| collection | DOAJ |
| description | In this article, we propose a nontraditional design of dynamic logic circuits using fully-depleted silicon-on-insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\text {t}}$ </tex-math></inline-formula>) to be adjustable (i.e., low-<inline-formula> <tex-math notation="LaTeX">$V_{\text {t}}$ </tex-math></inline-formula> and high-<inline-formula> <tex-math notation="LaTeX">$V_{\text {t}}$ </tex-math></inline-formula> states) by using the back gate (BG) bias. Our design utilizes the front gate (FG) and BG of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like a half-adder and full-adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14 nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product (PDP) of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge-sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates. |
| first_indexed | 2024-03-13T06:37:48Z |
| format | Article |
| id | doaj.art-1f65d10a88e6444f8c5229fc53be357c |
| institution | Directory Open Access Journal |
| issn | 2329-9231 |
| language | English |
| last_indexed | 2024-03-13T06:37:48Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj.art-1f65d10a88e6444f8c5229fc53be357c2023-06-08T23:01:45ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312023-01-0191748210.1109/JXCDC.2023.326914110106142Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient ComputingShubham Kumar0https://orcid.org/0000-0003-4228-9802Swetaki Chatterjee1https://orcid.org/0000-0002-2550-9626Chetan Kumar Dabhi2https://orcid.org/0000-0003-0795-4598Yogesh Singh Chauhan3https://orcid.org/0000-0002-3356-8917Hussam Amrouch4https://orcid.org/0000-0002-5649-3102Chair of Semiconductor Test and Reliability (STAR), University of Stuttgart, Stuttgart, GermanyChair of Semiconductor Test and Reliability (STAR), University of Stuttgart, Stuttgart, GermanyDepartment of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA, USADepartment of Electrical Engineering, IIT Kanpur, Kanpur, Uttar Pradesh, IndiaChair of AI Processor Design, Technical University of Munich (TUM), Munich, GermanyIn this article, we propose a nontraditional design of dynamic logic circuits using fully-depleted silicon-on-insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\text {t}}$ </tex-math></inline-formula>) to be adjustable (i.e., low-<inline-formula> <tex-math notation="LaTeX">$V_{\text {t}}$ </tex-math></inline-formula> and high-<inline-formula> <tex-math notation="LaTeX">$V_{\text {t}}$ </tex-math></inline-formula> states) by using the back gate (BG) bias. Our design utilizes the front gate (FG) and BG of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like a half-adder and full-adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14 nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product (PDP) of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge-sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates.https://ieeexplore.ieee.org/document/10106142/Charge sharingdynamic logic gatesfull-adderfully depleted silicon on insulator (FDSOI) FETshalf-addervariability |
| spellingShingle | Shubham Kumar Swetaki Chatterjee Chetan Kumar Dabhi Yogesh Singh Chauhan Hussam Amrouch Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Charge sharing dynamic logic gates full-adder fully depleted silicon on insulator (FDSOI) FETs half-adder variability |
| title | Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing |
| title_full | Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing |
| title_fullStr | Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing |
| title_full_unstemmed | Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing |
| title_short | Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing |
| title_sort | nontraditional design of dynamic logics using fdsoi for ultra efficient computing |
| topic | Charge sharing dynamic logic gates full-adder fully depleted silicon on insulator (FDSOI) FETs half-adder variability |
| url | https://ieeexplore.ieee.org/document/10106142/ |
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