Design and Implementation of a High Speed and Low Cost Hybrid FPS/LNS Processor Using FPGA
In the world of the computer data processing there are two main groups of processors first the microprocessor group that use the floating point system (FPS) and the TMS processor group that use logarithmic number system (LNS). There are many works and ideas to improve the two types and mixed betwee...
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| Format: | Article |
| Language: | Arabic |
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Mustansiriyah University/College of Engineering
2010-09-01
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| Series: | Journal of Engineering and Sustainable Development |
| Subjects: | |
| Online Access: | https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1467 |
| _version_ | 1818468496099508224 |
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| author | Dhafer R. Zaghar |
| author_facet | Dhafer R. Zaghar |
| author_sort | Dhafer R. Zaghar |
| collection | DOAJ |
| description |
In the world of the computer data processing there are two main groups of processors first the microprocessor group that use the floating point system (FPS) and the TMS processor group that use logarithmic number system (LNS). There are many works and ideas to improve the two types and mixed between them but the main drawback of these works is that "there are no common rules to measure the efficiency of each work and compare between them". This paper presents some logical and fair rules to measure the efficiency of the processor as a first step on the true way to implement a good process. Hence, this way has three main phases. First, classify the mathematics operations and deduce the approximation weight of each operation in the computer data processing such as general digital signal processing (DSP) fields, fast Fourier transform (FFT), filtering and neural network (NN). The second phase is proposing the design of an optimal process that has a high speed and low cost. The third phase is modifying the optimal design to implement it in the field programmable gate array (FPGA) media.
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| first_indexed | 2024-04-13T21:13:00Z |
| format | Article |
| id | doaj.art-1f6fb96672f74e16a795fff72c380bf4 |
| institution | Directory Open Access Journal |
| issn | 2520-0917 2520-0925 |
| language | Arabic |
| last_indexed | 2024-04-13T21:13:00Z |
| publishDate | 2010-09-01 |
| publisher | Mustansiriyah University/College of Engineering |
| record_format | Article |
| series | Journal of Engineering and Sustainable Development |
| spelling | doaj.art-1f6fb96672f74e16a795fff72c380bf42022-12-22T02:29:47ZaraMustansiriyah University/College of EngineeringJournal of Engineering and Sustainable Development2520-09172520-09252010-09-01143Design and Implementation of a High Speed and Low Cost Hybrid FPS/LNS Processor Using FPGADhafer R. Zaghar0Computer & Software Engineering Department, Al-Mustansiriyah University, Baghdad, Iraq In the world of the computer data processing there are two main groups of processors first the microprocessor group that use the floating point system (FPS) and the TMS processor group that use logarithmic number system (LNS). There are many works and ideas to improve the two types and mixed between them but the main drawback of these works is that "there are no common rules to measure the efficiency of each work and compare between them". This paper presents some logical and fair rules to measure the efficiency of the processor as a first step on the true way to implement a good process. Hence, this way has three main phases. First, classify the mathematics operations and deduce the approximation weight of each operation in the computer data processing such as general digital signal processing (DSP) fields, fast Fourier transform (FFT), filtering and neural network (NN). The second phase is proposing the design of an optimal process that has a high speed and low cost. The third phase is modifying the optimal design to implement it in the field programmable gate array (FPGA) media. https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1467Floating pointLNSDSPFFTNNFPGA |
| spellingShingle | Dhafer R. Zaghar Design and Implementation of a High Speed and Low Cost Hybrid FPS/LNS Processor Using FPGA Journal of Engineering and Sustainable Development Floating point LNS DSP FFT NN FPGA |
| title | Design and Implementation of a High Speed and Low Cost Hybrid FPS/LNS Processor Using FPGA |
| title_full | Design and Implementation of a High Speed and Low Cost Hybrid FPS/LNS Processor Using FPGA |
| title_fullStr | Design and Implementation of a High Speed and Low Cost Hybrid FPS/LNS Processor Using FPGA |
| title_full_unstemmed | Design and Implementation of a High Speed and Low Cost Hybrid FPS/LNS Processor Using FPGA |
| title_short | Design and Implementation of a High Speed and Low Cost Hybrid FPS/LNS Processor Using FPGA |
| title_sort | design and implementation of a high speed and low cost hybrid fps lns processor using fpga |
| topic | Floating point LNS DSP FFT NN FPGA |
| url | https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1467 |
| work_keys_str_mv | AT dhaferrzaghar designandimplementationofahighspeedandlowcosthybridfpslnsprocessorusingfpga |