Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme
Binary neural networks (BNNs) have attracted significant interest for the implementation of deep neural networks (DNNs) on resource-constrained edge devices, and various BNN accelerator architectures have been proposed to achieve higher efficiency. BNN accelerators can be divided into two categories...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-01-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/3/230 |
| _version_ | 1797409236692500480 |
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| author | Jaechan Cho Yongchul Jung Seongjoo Lee Yunho Jung |
| author_facet | Jaechan Cho Yongchul Jung Seongjoo Lee Yunho Jung |
| author_sort | Jaechan Cho |
| collection | DOAJ |
| description | Binary neural networks (BNNs) have attracted significant interest for the implementation of deep neural networks (DNNs) on resource-constrained edge devices, and various BNN accelerator architectures have been proposed to achieve higher efficiency. BNN accelerators can be divided into two categories: streaming and layer accelerators. Although streaming accelerators designed for a specific BNN network topology provide high throughput, they are infeasible for various sensor applications in edge AI because of their complexity and inflexibility. In contrast, layer accelerators with reasonable resources can support various network topologies, but they operate with the same parallelism for all the layers of the BNN, which degrades throughput performance at certain layers. To overcome this problem, we propose a BNN accelerator with adaptive parallelism that offers high throughput performance in all layers. The proposed accelerator analyzes target layer parameters and operates with optimal parallelism using reasonable resources. In addition, this architecture is able to fully compute all types of BNN layers thanks to its reconfigurability, and it can achieve a higher area–speed efficiency than existing accelerators. In performance evaluation using state-of-the-art BNN topologies, the designed BNN accelerator achieved an area–speed efficiency 9.69 times higher than previous FPGA implementations and 24% higher than existing VLSI implementations for BNNs. |
| first_indexed | 2024-03-09T04:11:22Z |
| format | Article |
| id | doaj.art-20def13f3c4e4636ab7e96c5dc8ec796 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T04:11:22Z |
| publishDate | 2021-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-20def13f3c4e4636ab7e96c5dc8ec7962023-12-03T13:59:07ZengMDPI AGElectronics2079-92922021-01-0110323010.3390/electronics10030230Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism SchemeJaechan Cho0Yongchul Jung1Seongjoo Lee2Yunho Jung3School of Electronics and Information Engineering, Korea Aerospace University, Goyang-si 10540, KoreaSchool of Electronics and Information Engineering, Korea Aerospace University, Goyang-si 10540, KoreaThe Department of Information and Communication Engineering and Convergence Engineering for Intelligent Drone, Sejong University, Seoul 143-747, KoreaDepartment of Smart Drone Convergence, School of Electronics and Information Engineering, Korea Aerospace University, Goyang-si 10540, KoreaBinary neural networks (BNNs) have attracted significant interest for the implementation of deep neural networks (DNNs) on resource-constrained edge devices, and various BNN accelerator architectures have been proposed to achieve higher efficiency. BNN accelerators can be divided into two categories: streaming and layer accelerators. Although streaming accelerators designed for a specific BNN network topology provide high throughput, they are infeasible for various sensor applications in edge AI because of their complexity and inflexibility. In contrast, layer accelerators with reasonable resources can support various network topologies, but they operate with the same parallelism for all the layers of the BNN, which degrades throughput performance at certain layers. To overcome this problem, we propose a BNN accelerator with adaptive parallelism that offers high throughput performance in all layers. The proposed accelerator analyzes target layer parameters and operates with optimal parallelism using reasonable resources. In addition, this architecture is able to fully compute all types of BNN layers thanks to its reconfigurability, and it can achieve a higher area–speed efficiency than existing accelerators. In performance evaluation using state-of-the-art BNN topologies, the designed BNN accelerator achieved an area–speed efficiency 9.69 times higher than previous FPGA implementations and 24% higher than existing VLSI implementations for BNNs.https://www.mdpi.com/2079-9292/10/3/230artificial intelligence (AI)binary neural network (BNN)FPGAmachine learningpattern recognitionVLSI |
| spellingShingle | Jaechan Cho Yongchul Jung Seongjoo Lee Yunho Jung Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme Electronics artificial intelligence (AI) binary neural network (BNN) FPGA machine learning pattern recognition VLSI |
| title | Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme |
| title_full | Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme |
| title_fullStr | Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme |
| title_full_unstemmed | Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme |
| title_short | Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme |
| title_sort | reconfigurable binary neural network accelerator with adaptive parallelism scheme |
| topic | artificial intelligence (AI) binary neural network (BNN) FPGA machine learning pattern recognition VLSI |
| url | https://www.mdpi.com/2079-9292/10/3/230 |
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