Reducing the Number of Luts for Mealy FSMS with State Transformation
In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSM circuit is one of the most important characteristics used in logic syn...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Sciendo
2024-03-01
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| Series: | International Journal of Applied Mathematics and Computer Science |
| Subjects: | |
| Online Access: | https://doi.org/10.61822/amcs-2024-0012 |