AREA EFFICIENT FRACTIONAL SAMPLE RATE CONVERSION ARCHITECTURE FOR SOFTWARE DEFINED RADIOS
The modern software defined radios (SDRs) use complex signal processing algorithms to realize efficient wireless communication schemes. Several such algorithms require a specific symbol to sample ratio to be maintained. In this context the fractional rate converter (FRC) becomes a crucial block in t...
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| Format: | Article |
| Language: | English |
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ICT Academy of Tamil Nadu
2014-09-01
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| Series: | ICTACT Journal on Communication Technology |
| Subjects: | |
| Online Access: | http://ictactjournals.in/paper/IJCT_Paper_5_977_986.pdf |
| _version_ | 1828402031861170176 |
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| author | Latha Sahukar M. Madhavi Latha |
| author_facet | Latha Sahukar M. Madhavi Latha |
| author_sort | Latha Sahukar |
| collection | DOAJ |
| description | The modern software defined radios (SDRs) use complex signal processing algorithms to realize efficient wireless communication schemes. Several such algorithms require a specific symbol to sample ratio to be maintained. In this context the fractional rate converter (FRC) becomes a crucial block in the receiver part of SDR. The paper presents an area optimized dynamic FRC block, for low power SDR applications. The limitations of conventional cascaded interpolator and decimator architecture for FRC are also presented. Extending the SINC function interpolation based architecture; towards high area optimization and providing run time configuration with time register are presented. The area and speed analysis are carried with Xilinx FPGA synthesis tools. Only 15% area occupancy with maximum clock speed of 133 MHz are reported on Spartan-6 Lx45 Field Programmable Gate Array (FPGA). |
| first_indexed | 2024-12-10T09:54:52Z |
| format | Article |
| id | doaj.art-21d568beefa049ae8b40170d9ab0028d |
| institution | Directory Open Access Journal |
| issn | 0976-0091 2229-6948 |
| language | English |
| last_indexed | 2024-12-10T09:54:52Z |
| publishDate | 2014-09-01 |
| publisher | ICT Academy of Tamil Nadu |
| record_format | Article |
| series | ICTACT Journal on Communication Technology |
| spelling | doaj.art-21d568beefa049ae8b40170d9ab0028d2022-12-22T01:53:31ZengICT Academy of Tamil NaduICTACT Journal on Communication Technology0976-00912229-69482014-09-0153977986AREA EFFICIENT FRACTIONAL SAMPLE RATE CONVERSION ARCHITECTURE FOR SOFTWARE DEFINED RADIOSLatha Sahukar0M. Madhavi Latha1Department of Electronics and Communication Engineering, Aurora’s Technological and Research Institute, IndiaDepartment of Electronics and Communication Engineering, JNTUH College of Engineering Hyderabad, IndiaThe modern software defined radios (SDRs) use complex signal processing algorithms to realize efficient wireless communication schemes. Several such algorithms require a specific symbol to sample ratio to be maintained. In this context the fractional rate converter (FRC) becomes a crucial block in the receiver part of SDR. The paper presents an area optimized dynamic FRC block, for low power SDR applications. The limitations of conventional cascaded interpolator and decimator architecture for FRC are also presented. Extending the SINC function interpolation based architecture; towards high area optimization and providing run time configuration with time register are presented. The area and speed analysis are carried with Xilinx FPGA synthesis tools. Only 15% area occupancy with maximum clock speed of 133 MHz are reported on Spartan-6 Lx45 Field Programmable Gate Array (FPGA).http://ictactjournals.in/paper/IJCT_Paper_5_977_986.pdfDecimationInterpolationSample Rate ConversionFractional Rate Conversion |
| spellingShingle | Latha Sahukar M. Madhavi Latha AREA EFFICIENT FRACTIONAL SAMPLE RATE CONVERSION ARCHITECTURE FOR SOFTWARE DEFINED RADIOS ICTACT Journal on Communication Technology Decimation Interpolation Sample Rate Conversion Fractional Rate Conversion |
| title | AREA EFFICIENT FRACTIONAL SAMPLE RATE CONVERSION ARCHITECTURE FOR SOFTWARE DEFINED RADIOS |
| title_full | AREA EFFICIENT FRACTIONAL SAMPLE RATE CONVERSION ARCHITECTURE FOR SOFTWARE DEFINED RADIOS |
| title_fullStr | AREA EFFICIENT FRACTIONAL SAMPLE RATE CONVERSION ARCHITECTURE FOR SOFTWARE DEFINED RADIOS |
| title_full_unstemmed | AREA EFFICIENT FRACTIONAL SAMPLE RATE CONVERSION ARCHITECTURE FOR SOFTWARE DEFINED RADIOS |
| title_short | AREA EFFICIENT FRACTIONAL SAMPLE RATE CONVERSION ARCHITECTURE FOR SOFTWARE DEFINED RADIOS |
| title_sort | area efficient fractional sample rate conversion architecture for software defined radios |
| topic | Decimation Interpolation Sample Rate Conversion Fractional Rate Conversion |
| url | http://ictactjournals.in/paper/IJCT_Paper_5_977_986.pdf |
| work_keys_str_mv | AT lathasahukar areaefficientfractionalsamplerateconversionarchitectureforsoftwaredefinedradios AT mmadhavilatha areaefficientfractionalsamplerateconversionarchitectureforsoftwaredefinedradios |