An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder
HEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) ar...
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| Format: | Article |
| Language: | English |
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MDPI AG
2020-04-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/9/4/684 |
| _version_ | 1797569828773429248 |
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| author | Dinh-Lam Tran Xuan-Tu Tran Duy-Hieu Bui Cong-Kha Pham |
| author_facet | Dinh-Lam Tran Xuan-Tu Tran Duy-Hieu Bui Cong-Kha Pham |
| author_sort | Dinh-Lam Tran |
| collection | DOAJ |
| description | HEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) are generated to feed the binary arithmetic encoder (BAE). The residual video data occupied an average of 75% of the CABAC’s work-load, thus its performance will significantly contribute to the overall performance of whole CABAC design. This paper proposes an efficient hardware implementation of a binarizer for CABAC that focuses on low area cost, low power consumption while still providing enough bins for high-throughput CABAC. On the average, the proposed design can process upto 3.5 residual syntax elements (SEs) per clock cycle at the maximum frequency of 500 MHz with an area cost of 9.45 Kgates (6.41 Kgates for the binarizer core) and power consumption of 0.239 mW (0.184 mW for the binarizer core) with NanGate 45 nm technology. It shows that our proposal achieved a high overhead-efficiency of 1.293 Mbins/Kgate/mW, much better than the other related high performance designs. In addition, our design also achieved a high power-efficiency of 8288 Mbins/mW; this is important factor for handheld applications. |
| first_indexed | 2024-03-10T20:17:06Z |
| format | Article |
| id | doaj.art-22651f953cfc4f30b76591b1dc2e1af3 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T20:17:06Z |
| publishDate | 2020-04-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-22651f953cfc4f30b76591b1dc2e1af32023-11-19T22:27:36ZengMDPI AGElectronics2079-92922020-04-019468410.3390/electronics9040684An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC EncoderDinh-Lam Tran0Xuan-Tu Tran1Duy-Hieu Bui2Cong-Kha Pham3VNU Key Laboratory for Smart Integrated Systems (SISLAB), University of Engineering and Technology, Vietnam National University, Hanoi 123106, VietnamVNU Key Laboratory for Smart Integrated Systems (SISLAB), University of Engineering and Technology, Vietnam National University, Hanoi 123106, VietnamVNU Key Laboratory for Smart Integrated Systems (SISLAB), University of Engineering and Technology, Vietnam National University, Hanoi 123106, VietnamDepartment of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo 182-8585, JapanHEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) are generated to feed the binary arithmetic encoder (BAE). The residual video data occupied an average of 75% of the CABAC’s work-load, thus its performance will significantly contribute to the overall performance of whole CABAC design. This paper proposes an efficient hardware implementation of a binarizer for CABAC that focuses on low area cost, low power consumption while still providing enough bins for high-throughput CABAC. On the average, the proposed design can process upto 3.5 residual syntax elements (SEs) per clock cycle at the maximum frequency of 500 MHz with an area cost of 9.45 Kgates (6.41 Kgates for the binarizer core) and power consumption of 0.239 mW (0.184 mW for the binarizer core) with NanGate 45 nm technology. It shows that our proposal achieved a high overhead-efficiency of 1.293 Mbins/Kgate/mW, much better than the other related high performance designs. In addition, our design also achieved a high power-efficiency of 8288 Mbins/mW; this is important factor for handheld applications.https://www.mdpi.com/2079-9292/9/4/684HEVCCABACresidual data binarizationhardware implementation |
| spellingShingle | Dinh-Lam Tran Xuan-Tu Tran Duy-Hieu Bui Cong-Kha Pham An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder Electronics HEVC CABAC residual data binarization hardware implementation |
| title | An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder |
| title_full | An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder |
| title_fullStr | An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder |
| title_full_unstemmed | An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder |
| title_short | An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder |
| title_sort | efficient hardware implementation of residual data binarization in hevc cabac encoder |
| topic | HEVC CABAC residual data binarization hardware implementation |
| url | https://www.mdpi.com/2079-9292/9/4/684 |
| work_keys_str_mv | AT dinhlamtran anefficienthardwareimplementationofresidualdatabinarizationinhevccabacencoder AT xuantutran anefficienthardwareimplementationofresidualdatabinarizationinhevccabacencoder AT duyhieubui anefficienthardwareimplementationofresidualdatabinarizationinhevccabacencoder AT congkhapham anefficienthardwareimplementationofresidualdatabinarizationinhevccabacencoder AT dinhlamtran efficienthardwareimplementationofresidualdatabinarizationinhevccabacencoder AT xuantutran efficienthardwareimplementationofresidualdatabinarizationinhevccabacencoder AT duyhieubui efficienthardwareimplementationofresidualdatabinarizationinhevccabacencoder AT congkhapham efficienthardwareimplementationofresidualdatabinarizationinhevccabacencoder |