Noise‐based logic locking scheme against signal probability skew analysis
Abstract Due to integrated circuit (IC) production chain globalisation, several new threats such as hardware trojans, counterfeiting and overproduction are threatening the IC industry. So logic locking is deployed to hinder these security threats. In this technique, an IC is locked, and its function...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Hindawi-IET
2021-07-01
|
| Series: | IET Computers & Digital Techniques |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cdt2.12022 |
| _version_ | 1797429404159180800 |
|---|---|
| author | Ahmad Rezaei Ali Mahani |
| author_facet | Ahmad Rezaei Ali Mahani |
| author_sort | Ahmad Rezaei |
| collection | DOAJ |
| description | Abstract Due to integrated circuit (IC) production chain globalisation, several new threats such as hardware trojans, counterfeiting and overproduction are threatening the IC industry. So logic locking is deployed to hinder these security threats. In this technique, an IC is locked, and its functionality is retrieved when the right key is loaded onto it. We propose ‘noise‐based’ logic locking, consisting of two separate compliment blocks, which function in three states. By flipping a signal once in the circuit, these modules add corruption to the circuit, whereas either flipping the same signal twice or not flipping leads to the correct functionality. Thus, a low probability skew with a low corruption in the output is obtained by utilisation of these flipping states. We have improved SAT attack resiliency based on time by 17% for a locking block with 14 primary inputs in comparison with the well‐known anti‐SAT. The area overhead is less in comparison with other schemes, in which extra dummy parts or obfuscation elements are added to their circuit. Also, more crucially, our locking blocks are immune to SPS attack solely. After executing various attacks, retrieved circuits indicate improved overall resiliency against automatic test pattern generation based and approximate guided removal attacks as well. |
| first_indexed | 2024-03-09T09:12:41Z |
| format | Article |
| id | doaj.art-22b8852256d24300804b4a0b518a9b8b |
| institution | Directory Open Access Journal |
| issn | 1751-8601 1751-861X |
| language | English |
| last_indexed | 2024-03-09T09:12:41Z |
| publishDate | 2021-07-01 |
| publisher | Hindawi-IET |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj.art-22b8852256d24300804b4a0b518a9b8b2023-12-02T07:58:36ZengHindawi-IETIET Computers & Digital Techniques1751-86011751-861X2021-07-0115427929510.1049/cdt2.12022Noise‐based logic locking scheme against signal probability skew analysisAhmad Rezaei0Ali Mahani1Department of Electrical Engineering Reliable & Smart Systems Laboratory Shahid Bahonar University of Kerman Kerman IranDepartment of Electrical Engineering Reliable & Smart Systems Laboratory Shahid Bahonar University of Kerman Kerman IranAbstract Due to integrated circuit (IC) production chain globalisation, several new threats such as hardware trojans, counterfeiting and overproduction are threatening the IC industry. So logic locking is deployed to hinder these security threats. In this technique, an IC is locked, and its functionality is retrieved when the right key is loaded onto it. We propose ‘noise‐based’ logic locking, consisting of two separate compliment blocks, which function in three states. By flipping a signal once in the circuit, these modules add corruption to the circuit, whereas either flipping the same signal twice or not flipping leads to the correct functionality. Thus, a low probability skew with a low corruption in the output is obtained by utilisation of these flipping states. We have improved SAT attack resiliency based on time by 17% for a locking block with 14 primary inputs in comparison with the well‐known anti‐SAT. The area overhead is less in comparison with other schemes, in which extra dummy parts or obfuscation elements are added to their circuit. Also, more crucially, our locking blocks are immune to SPS attack solely. After executing various attacks, retrieved circuits indicate improved overall resiliency against automatic test pattern generation based and approximate guided removal attacks as well.https://doi.org/10.1049/cdt2.12022automatic test pattern generationprobabilityinvasive softwareintegrated circuit testingcircuit noiselogic circuits |
| spellingShingle | Ahmad Rezaei Ali Mahani Noise‐based logic locking scheme against signal probability skew analysis IET Computers & Digital Techniques automatic test pattern generation probability invasive software integrated circuit testing circuit noise logic circuits |
| title | Noise‐based logic locking scheme against signal probability skew analysis |
| title_full | Noise‐based logic locking scheme against signal probability skew analysis |
| title_fullStr | Noise‐based logic locking scheme against signal probability skew analysis |
| title_full_unstemmed | Noise‐based logic locking scheme against signal probability skew analysis |
| title_short | Noise‐based logic locking scheme against signal probability skew analysis |
| title_sort | noise based logic locking scheme against signal probability skew analysis |
| topic | automatic test pattern generation probability invasive software integrated circuit testing circuit noise logic circuits |
| url | https://doi.org/10.1049/cdt2.12022 |
| work_keys_str_mv | AT ahmadrezaei noisebasedlogiclockingschemeagainstsignalprobabilityskewanalysis AT alimahani noisebasedlogiclockingschemeagainstsignalprobabilityskewanalysis |