Temporal Accelerators: Unleashing the Potential of Embedded FPGAs

When the complexity of a problem rises, its solution requires more hardware resources. A usual way to solve this is to use larger processors and add more memory. When using Field Programmable Gate-Arrays (FPGAs), which can instantiate arbitrary circuit designs, a larger, mo...

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Main Authors: Christopher Cichiwskyj, Gregor Schiele
Format: Article
Language:English
Published: Graz University of Technology 2021-11-01
Series:Journal of Universal Computer Science
Subjects:
Online Access:https://lib.jucs.org/article/77247/download/pdf/
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author Christopher Cichiwskyj
Gregor Schiele
author_facet Christopher Cichiwskyj
Gregor Schiele
author_sort Christopher Cichiwskyj
collection DOAJ
description When the complexity of a problem rises, its solution requires more hardware resources. A usual way to solve this is to use larger processors and add more memory. When using Field Programmable Gate-Arrays (FPGAs), which can instantiate arbitrary circuit designs, a larger, more costly and power hungry chip is used. In this paper we propose a different approach, namely to split the problem into a graph of interdependent smaller tasks and to reconfigure a small FPGA during runtime to execute each of these tasks efficiently sequentially. This can result in cheaper and more energy efficient systems that can execute very complex problems locally. We present a basic analytical model, evaluate its accuracy and discuss initial insight from it.
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spelling doaj.art-24ff81af55b0430dbcd8f0816bee418a2022-12-21T19:26:28ZengGraz University of TechnologyJournal of Universal Computer Science0948-69682021-11-0127111174119210.3897/jucs.7724777247Temporal Accelerators: Unleashing the Potential of Embedded FPGAsChristopher Cichiwskyj0Gregor Schiele1Universität Duisburg-EssenUniversität Duisburg-EssenWhen the complexity of a problem rises, its solution requires more hardware resources. A usual way to solve this is to use larger processors and add more memory. When using Field Programmable Gate-Arrays (FPGAs), which can instantiate arbitrary circuit designs, a larger, more costly and power hungry chip is used. In this paper we propose a different approach, namely to split the problem into a graph of interdependent smaller tasks and to reconfigure a small FPGA during runtime to execute each of these tasks efficiently sequentially. This can result in cheaper and more energy efficient systems that can execute very complex problems locally. We present a basic analytical model, evaluate its accuracy and discuss initial insight from it.https://lib.jucs.org/article/77247/download/pdf/IoTEmbeddedFPGAReconfigurable Hardware
spellingShingle Christopher Cichiwskyj
Gregor Schiele
Temporal Accelerators: Unleashing the Potential of Embedded FPGAs
Journal of Universal Computer Science
IoT
Embedded
FPGA
Reconfigurable Hardware
title Temporal Accelerators: Unleashing the Potential of Embedded FPGAs
title_full Temporal Accelerators: Unleashing the Potential of Embedded FPGAs
title_fullStr Temporal Accelerators: Unleashing the Potential of Embedded FPGAs
title_full_unstemmed Temporal Accelerators: Unleashing the Potential of Embedded FPGAs
title_short Temporal Accelerators: Unleashing the Potential of Embedded FPGAs
title_sort temporal accelerators unleashing the potential of embedded fpgas
topic IoT
Embedded
FPGA
Reconfigurable Hardware
url https://lib.jucs.org/article/77247/download/pdf/
work_keys_str_mv AT christophercichiwskyj temporalacceleratorsunleashingthepotentialofembeddedfpgas
AT gregorschiele temporalacceleratorsunleashingthepotentialofembeddedfpgas