A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmission
We propose a CMOS image sensor with a dedicated low-power imaging mode and low-power integrated transmitter. The proposed CMOS image sensor selectively operates in dual mode: a high-quality mode with a 1.5 V supply voltage of readout circuits to achieve a high signal-to-noise ratio (SNR), and a low-...
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| Format: | Article |
| Language: | English |
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IEEE
2022-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9893821/ |
| _version_ | 1811264814948810752 |
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| author | Sang-Hoon Kim Yongsung Cho Jiwon Lee Jung-Hoon Chun Jaehyuk Choi |
| author_facet | Sang-Hoon Kim Yongsung Cho Jiwon Lee Jung-Hoon Chun Jaehyuk Choi |
| author_sort | Sang-Hoon Kim |
| collection | DOAJ |
| description | We propose a CMOS image sensor with a dedicated low-power imaging mode and low-power integrated transmitter. The proposed CMOS image sensor selectively operates in dual mode: a high-quality mode with a 1.5 V supply voltage of readout circuits to achieve a high signal-to-noise ratio (SNR), and a low-power mode with a 0.9 V supply voltage to support always-on imaging. To further reduce the power consumption in the low-power mode, a single-slope analog to digital converter (ADC) embeds a power cutoff scheme in the comparator and a two-step conversion with dual reference voltages. To alleviate the SNR degradation in the low-power mode, which inherently occurs from voltage scaling, a correlated multiple sampling technique that consumes negligible power overhead is implemented using the proposed window-counting scheme. To reduce the significant power consumption that occurs during image signal transmission, an integrated transmitter with four-stacked charge-recycling drivers is used so that four symbols are simultaneously transmitted with a shared supply voltage. A prototype CMOS image sensor with 680 <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 520 pixels is fabricated using 110-nm CMOS image sensor technology. The fabricated CMOS image sensor consumes only <inline-formula> <tex-math notation="LaTeX">$301~\mu \text{W}$ </tex-math></inline-formula> (at 15 fps) in the sensor core and 2.03 mW including the transmitter and phase locked loop (PLL) while generating low temporal random noise under 0.27 LSB with correlated multiple sampling. |
| first_indexed | 2024-04-12T20:11:12Z |
| format | Article |
| id | doaj.art-25167be932254b52acfa0bb66064cbff |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-12T20:11:12Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-25167be932254b52acfa0bb66064cbff2022-12-22T03:18:14ZengIEEEIEEE Access2169-35362022-01-0110995539956110.1109/ACCESS.2022.32072989893821A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal TransmissionSang-Hoon Kim0Yongsung Cho1https://orcid.org/0000-0002-8488-272XJiwon Lee2https://orcid.org/0000-0003-3738-4872Jung-Hoon Chun3https://orcid.org/0000-0002-2668-6739Jaehyuk Choi4https://orcid.org/0000-0003-4700-1900College of Information & Communication Engineering, Sungkyunkwan University, Suwon, Republic of KoreaCollege of Information & Communication Engineering, Sungkyunkwan University, Suwon, Republic of KoreaIMEC, Leuven, BelgiumCollege of Information & Communication Engineering, Sungkyunkwan University, Suwon, Republic of KoreaCollege of Information & Communication Engineering, Sungkyunkwan University, Suwon, Republic of KoreaWe propose a CMOS image sensor with a dedicated low-power imaging mode and low-power integrated transmitter. The proposed CMOS image sensor selectively operates in dual mode: a high-quality mode with a 1.5 V supply voltage of readout circuits to achieve a high signal-to-noise ratio (SNR), and a low-power mode with a 0.9 V supply voltage to support always-on imaging. To further reduce the power consumption in the low-power mode, a single-slope analog to digital converter (ADC) embeds a power cutoff scheme in the comparator and a two-step conversion with dual reference voltages. To alleviate the SNR degradation in the low-power mode, which inherently occurs from voltage scaling, a correlated multiple sampling technique that consumes negligible power overhead is implemented using the proposed window-counting scheme. To reduce the significant power consumption that occurs during image signal transmission, an integrated transmitter with four-stacked charge-recycling drivers is used so that four symbols are simultaneously transmitted with a shared supply voltage. A prototype CMOS image sensor with 680 <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 520 pixels is fabricated using 110-nm CMOS image sensor technology. The fabricated CMOS image sensor consumes only <inline-formula> <tex-math notation="LaTeX">$301~\mu \text{W}$ </tex-math></inline-formula> (at 15 fps) in the sensor core and 2.03 mW including the transmitter and phase locked loop (PLL) while generating low temporal random noise under 0.27 LSB with correlated multiple sampling.https://ieeexplore.ieee.org/document/9893821/CMOS image sensorcorrelated-multiple-sampling (CMS)dual-modelow-powerpower reduction techniques |
| spellingShingle | Sang-Hoon Kim Yongsung Cho Jiwon Lee Jung-Hoon Chun Jaehyuk Choi A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmission IEEE Access CMOS image sensor correlated-multiple-sampling (CMS) dual-mode low-power power reduction techniques |
| title | A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmission |
| title_full | A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmission |
| title_fullStr | A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmission |
| title_full_unstemmed | A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmission |
| title_short | A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmission |
| title_sort | 2 03 mw cmos image sensor with an integrated four stacked charge recycling driver for image signal transmission |
| topic | CMOS image sensor correlated-multiple-sampling (CMS) dual-mode low-power power reduction techniques |
| url | https://ieeexplore.ieee.org/document/9893821/ |
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