Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration
In this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for a neural seizure detection application. The training accelerator algorithm, adopted in this work, is the sequential minimal optimization (SMO). Sy...
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IEEE
2021-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9427493/ |
| _version_ | 1818573950199791616 |
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| author | Heba Elhosary Michael H. Zakhari Mohamed A. Elgammal Khaled A. Helal Kelany Mohamed A. Abd El Ghany Khaled N. Salama Hassan Mostafa |
| author_facet | Heba Elhosary Michael H. Zakhari Mohamed A. Elgammal Khaled A. Helal Kelany Mohamed A. Abd El Ghany Khaled N. Salama Hassan Mostafa |
| author_sort | Heba Elhosary |
| collection | DOAJ |
| description | In this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for a neural seizure detection application. The training accelerator algorithm, adopted in this work, is the sequential minimal optimization (SMO). System blocks are implemented to achieve the best trade-off between sensitivity and the consumption of area and power. The proposed seizure detection system achieves 98.38% sensitivity when tested with the implemented linear kernel classifier. The system is implemented on different platforms: such as Field Programmable Gate Array (FPGA) Xilinx Virtex-7 board and Application Specific Integrated Circuit (ASIC) using hardware-calibrated UMC 65nm CMOS technology. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is lower by at least 65% when compared with the FPGA counterpart. A power-aware system is implemented with FPGAs by the adoption of the Dynamic Partial Reconfiguration (DPR) technique that allows the dynamic operation of the system based on power level available to the system at the expense of degradation of the system accuracy. The proposed system exploits the advantages of DPR technology in FPGAs to switch between two proposed designs providing a decrease of 64% in power consumption. |
| first_indexed | 2024-12-15T00:19:55Z |
| format | Article |
| id | doaj.art-26cb9b3ba72d487792334caeba88a8d0 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-15T00:19:55Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-26cb9b3ba72d487792334caeba88a8d02022-12-21T22:42:20ZengIEEEIEEE Access2169-35362021-01-019750717508110.1109/ACCESS.2021.30791559427493Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial ReconfigurationHeba Elhosary0Michael H. Zakhari1Mohamed A. Elgammal2https://orcid.org/0000-0001-8555-7331Khaled A. Helal Kelany3Mohamed A. Abd El Ghany4https://orcid.org/0000-0002-6282-7738Khaled N. Salama5https://orcid.org/0000-0001-7742-1282Hassan Mostafa6https://orcid.org/0000-0003-0043-5007Department of Electronics, German University in Cairo (GUC), New Cairo, EgyptDepartment of Electronics and Communications Engineering, Cairo University, Giza, EgyptDepartment of Electronics and Communications Engineering, Cairo University, Giza, EgyptDepartment of Electronics and Communications Engineering, Cairo University, Giza, EgyptDepartment of Electronics, German University in Cairo (GUC), New Cairo, EgyptElectrical and Mathematical Science and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal, Computer, Saudi ArabiaDepartment of Electronics and Communications Engineering, Cairo University, Giza, EgyptIn this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for a neural seizure detection application. The training accelerator algorithm, adopted in this work, is the sequential minimal optimization (SMO). System blocks are implemented to achieve the best trade-off between sensitivity and the consumption of area and power. The proposed seizure detection system achieves 98.38% sensitivity when tested with the implemented linear kernel classifier. The system is implemented on different platforms: such as Field Programmable Gate Array (FPGA) Xilinx Virtex-7 board and Application Specific Integrated Circuit (ASIC) using hardware-calibrated UMC 65nm CMOS technology. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is lower by at least 65% when compared with the FPGA counterpart. A power-aware system is implemented with FPGAs by the adoption of the Dynamic Partial Reconfiguration (DPR) technique that allows the dynamic operation of the system based on power level available to the system at the expense of degradation of the system accuracy. The proposed system exploits the advantages of DPR technology in FPGAs to switch between two proposed designs providing a decrease of 64% in power consumption.https://ieeexplore.ieee.org/document/9427493/Low powersupport vector machine (SVM)sequential minimal optimization (SMO)accelerator IPfeature extractionclassification |
| spellingShingle | Heba Elhosary Michael H. Zakhari Mohamed A. Elgammal Khaled A. Helal Kelany Mohamed A. Abd El Ghany Khaled N. Salama Hassan Mostafa Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration IEEE Access Low power support vector machine (SVM) sequential minimal optimization (SMO) accelerator IP feature extraction classification |
| title | Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration |
| title_full | Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration |
| title_fullStr | Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration |
| title_full_unstemmed | Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration |
| title_short | Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration |
| title_sort | hardware acceleration of high sensitivity power aware epileptic seizure detection system using dynamic partial reconfiguration |
| topic | Low power support vector machine (SVM) sequential minimal optimization (SMO) accelerator IP feature extraction classification |
| url | https://ieeexplore.ieee.org/document/9427493/ |
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