A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform
Software-defined networking has been developing in recent years and the separation of the control plane and the data plane has made networks more flexible. Due to its flexibility, the software method is used to implement the data plane. However, with increasing network speed, the CPU is becoming una...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-10-01
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| Series: | Micromachines |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2072-666X/13/11/1854 |
| _version_ | 1797467223490560000 |
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| author | Meng Sha Zhichuan Guo Yunfei Guo Xuewen Zeng |
| author_facet | Meng Sha Zhichuan Guo Yunfei Guo Xuewen Zeng |
| author_sort | Meng Sha |
| collection | DOAJ |
| description | Software-defined networking has been developing in recent years and the separation of the control plane and the data plane has made networks more flexible. Due to its flexibility, the software method is used to implement the data plane. However, with increasing network speed, the CPU is becoming unable to meet the requirements of high-speed packet processing. FPGAs are usually used as dumb switches to accelerate the data plane, with all intelligence centralized in the remote controller. However, the cost of taking the intelligence out of the switch is the increased latency between the controller and the switch. Therefore, we argue that the control decisions should be made as locally as possible. In this paper, we propose a novel architecture with high performance and flexibility for accelerating SDN based on the MPSoC platform. The control plane is implemented in the on-chip CPU and the data plane is implemented in the FPGA logic. The communication between the two components is performed using Ethernet communication. We design a high-performance TCAM based on distributed RAM. The architecture employs a pipeline design with modules connected via the AXI Stream interface. The designed architecture is flexible enough to support multiple network functions while achieving high performance at 100 Gbps. As far as we know, the architecture is the first proposed in the design of a 100 Gbps system. |
| first_indexed | 2024-03-09T18:49:41Z |
| format | Article |
| id | doaj.art-281c2eeea3ee4e178e20ccd17593b64a |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-09T18:49:41Z |
| publishDate | 2022-10-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-281c2eeea3ee4e178e20ccd17593b64a2023-11-24T05:54:13ZengMDPI AGMicromachines2072-666X2022-10-011311185410.3390/mi13111854A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC PlatformMeng Sha0Zhichuan Guo1Yunfei Guo2Xuewen Zeng3National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, ChinaNational Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, ChinaNational Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, ChinaNational Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, ChinaSoftware-defined networking has been developing in recent years and the separation of the control plane and the data plane has made networks more flexible. Due to its flexibility, the software method is used to implement the data plane. However, with increasing network speed, the CPU is becoming unable to meet the requirements of high-speed packet processing. FPGAs are usually used as dumb switches to accelerate the data plane, with all intelligence centralized in the remote controller. However, the cost of taking the intelligence out of the switch is the increased latency between the controller and the switch. Therefore, we argue that the control decisions should be made as locally as possible. In this paper, we propose a novel architecture with high performance and flexibility for accelerating SDN based on the MPSoC platform. The control plane is implemented in the on-chip CPU and the data plane is implemented in the FPGA logic. The communication between the two components is performed using Ethernet communication. We design a high-performance TCAM based on distributed RAM. The architecture employs a pipeline design with modules connected via the AXI Stream interface. The designed architecture is flexible enough to support multiple network functions while achieving high performance at 100 Gbps. As far as we know, the architecture is the first proposed in the design of a 100 Gbps system.https://www.mdpi.com/2072-666X/13/11/1854SDNnetwork accelerationFPGAreprogrammable hardware |
| spellingShingle | Meng Sha Zhichuan Guo Yunfei Guo Xuewen Zeng A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform Micromachines SDN network acceleration FPGA reprogrammable hardware |
| title | A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform |
| title_full | A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform |
| title_fullStr | A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform |
| title_full_unstemmed | A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform |
| title_short | A High-Performance and Flexible Architecture for Accelerating SDN on the MPSoC Platform |
| title_sort | high performance and flexible architecture for accelerating sdn on the mpsoc platform |
| topic | SDN network acceleration FPGA reprogrammable hardware |
| url | https://www.mdpi.com/2072-666X/13/11/1854 |
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