Power Optimization For Multi-Core Memory Controller Using Intelligent Clock Gating Technique
The demand for low-power digital systems is increasing daily, especially for the multi-core design on SoC. Different IP cores of the existing multi-core memory controller need to communicate to achieve specific tasks on the same die. The system clock toggles each synchronous part of the multi-core m...
| Príomhchruthaitheoirí: | , , |
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| Formáid: | Alt |
| Teanga: | English |
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Editura Universităţii din Oradea
2022-10-01
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| Sraith: | Journal of Electrical and Electronics Engineering |
| Ábhair: | |
| Rochtain ar líne: | http://electroinf.uoradea.ro/images/articles/CERCETARE/Reviste/JEEE/JEEE_V15_N2_OCT_2022/NOAMI_JEEE.pdf |
| Achoimre: | The demand for low-power digital systems is increasing daily, especially for the multi-core design on SoC. Different IP cores of the existing multi-core memory controller need to communicate to achieve specific tasks on the same die. The system clock toggles each synchronous part of the multi-core memory controller system during the communication among different IPs. However, some synchronous parts of the multi-core memory controller system are not used at all the system clock time, leading to more dynamic power dissipation. In this paper, the intelligent clock gating (ICG) optimization technique is used to avoid unnecessary switching activity for different synchronous parts of the multi-core memory controller system, decrease the dynamic power, and improve the entire performance of the multi-core memory controller system. The dynamic power improvement for different multi-core memory controller systems is 26.32%, 30.43%, 33.33%, and 27.30% compared with the existing systems. The Multi-core memory controllers without/ with intelligent clock gating technique are successfully synthesized and implemented using the Vivado tool 2018.1 and FPGA ZedBoard (xc7z020clg484-l). |
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| ISSN: | 1844-6035 2067-2128 |