Power Optimization For Multi-Core Memory Controller Using Intelligent Clock Gating Technique

Power Optimization For Multi-Core Memory Controller Using Intelligent Clock Gating Technique

The demand for low-power digital systems is increasing daily, especially for the multi-core design on SoC. Different IP cores of the existing multi-core memory controller need to communicate to achieve specific tasks on the same die. The system clock toggles each synchronous part of the multi-core m...

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Detalles Bibliográficos
Main Authors: NOAMI Ahmed, KUMAR PRADEEP Boya, SEKHAR PAIDIMARRY Chandra
Formato: Artigo
Idioma:English
Publicado: Editura Universităţii din Oradea 2022-10-01
Series:Journal of Electrical and Electronics Engineering
Subjects:
clock gating
dynamic power
ip cores
multi-core system
memory controller
Acceso en liña:http://electroinf.uoradea.ro/images/articles/CERCETARE/Reviste/JEEE/JEEE_V15_N2_OCT_2022/NOAMI_JEEE.pdf

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