Power Optimization For Multi-Core Memory Controller Using Intelligent Clock Gating Technique
The demand for low-power digital systems is increasing daily, especially for the multi-core design on SoC. Different IP cores of the existing multi-core memory controller need to communicate to achieve specific tasks on the same die. The system clock toggles each synchronous part of the multi-core m...
| Հիմնական հեղինակներ: | , , |
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| Ձևաչափ: | Հոդված |
| Լեզու: | English |
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Editura Universităţii din Oradea
2022-10-01
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| Շարք: | Journal of Electrical and Electronics Engineering |
| Խորագրեր: | |
| Առցանց հասանելիություն: | http://electroinf.uoradea.ro/images/articles/CERCETARE/Reviste/JEEE/JEEE_V15_N2_OCT_2022/NOAMI_JEEE.pdf |