Power Optimization For Multi-Core Memory Controller Using Intelligent Clock Gating Technique
The demand for low-power digital systems is increasing daily, especially for the multi-core design on SoC. Different IP cores of the existing multi-core memory controller need to communicate to achieve specific tasks on the same die. The system clock toggles each synchronous part of the multi-core m...
| Main Authors: | , , |
|---|---|
| 格式: | Article |
| 語言: | English |
| 出版: |
Editura Universităţii din Oradea
2022-10-01
|
| 叢編: | Journal of Electrical and Electronics Engineering |
| 主題: | |
| 在線閱讀: | http://electroinf.uoradea.ro/images/articles/CERCETARE/Reviste/JEEE/JEEE_V15_N2_OCT_2022/NOAMI_JEEE.pdf |