Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions
This paper proposes data-dependent reliability evaluation methodology for digital systems described at Register Transfer Level (RTL). It uses a hybrid hierarchical approach, combining the accuracy provided by Gate Level (GL) Simulated Fault Injection (SFI) and the low simulation overhead required...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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Stefan cel Mare University of Suceava
2016-02-01
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| Series: | Advances in Electrical and Computer Engineering |
| Subjects: | |
| Online Access: | http://dx.doi.org/10.4316/AECE.2016.01013 |
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| author | NIMARA, S. AMARICAI, A. BONCALO, O. POPA, M. |
| author_facet | NIMARA, S. AMARICAI, A. BONCALO, O. POPA, M. |
| author_sort | NIMARA, S. |
| collection | DOAJ |
| description | This paper proposes data-dependent reliability evaluation methodology for digital systems described at Register
Transfer Level (RTL). It uses a hybrid hierarchical approach, combining the accuracy provided by Gate Level (GL)
Simulated Fault Injection (SFI) and the low simulation overhead required by RTL fault injection. The methodology
comprises the following steps: the correct simulation of the RTL system, according to a set of input vectors,
hierarchical decomposition of the system into basic RTL blocks, logic synthesis of basic RTL blocks, data-dependent
SFI for the GL netlists, and RTL SFI. The proposed methodology has been validated in terms of accuracy on a medium
sized circuit – the parallel comparator used in Check Node Unit (CNU) of the Low-Density Parity-Check (LDPC) decoders.
The methodology has been applied for the reliability analysis of a 128-bit Advanced Encryption Standard (AES)
crypto-core, for which the GL simulation was prohibitive in terms of required computational resources. |
| first_indexed | 2024-12-24T03:49:24Z |
| format | Article |
| id | doaj.art-299c27f463e34537906996b127a4a723 |
| institution | Directory Open Access Journal |
| issn | 1582-7445 1844-7600 |
| language | English |
| last_indexed | 2024-12-24T03:49:24Z |
| publishDate | 2016-02-01 |
| publisher | Stefan cel Mare University of Suceava |
| record_format | Article |
| series | Advances in Electrical and Computer Engineering |
| spelling | doaj.art-299c27f463e34537906996b127a4a7232022-12-21T17:16:37ZengStefan cel Mare University of SuceavaAdvances in Electrical and Computer Engineering1582-74451844-76002016-02-01161939810.4316/AECE.2016.01013Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit DescriptionsNIMARA, S.AMARICAI, A.BONCALO, O.POPA, M.This paper proposes data-dependent reliability evaluation methodology for digital systems described at Register Transfer Level (RTL). It uses a hybrid hierarchical approach, combining the accuracy provided by Gate Level (GL) Simulated Fault Injection (SFI) and the low simulation overhead required by RTL fault injection. The methodology comprises the following steps: the correct simulation of the RTL system, according to a set of input vectors, hierarchical decomposition of the system into basic RTL blocks, logic synthesis of basic RTL blocks, data-dependent SFI for the GL netlists, and RTL SFI. The proposed methodology has been validated in terms of accuracy on a medium sized circuit – the parallel comparator used in Check Node Unit (CNU) of the Low-Density Parity-Check (LDPC) decoders. The methodology has been applied for the reliability analysis of a 128-bit Advanced Encryption Standard (AES) crypto-core, for which the GL simulation was prohibitive in terms of required computational resources.http://dx.doi.org/10.4316/AECE.2016.01013digital circuitsprobabilistic circuitsregister transfer levelreliabilitysimulated fault injection |
| spellingShingle | NIMARA, S. AMARICAI, A. BONCALO, O. POPA, M. Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions Advances in Electrical and Computer Engineering digital circuits probabilistic circuits register transfer level reliability simulated fault injection |
| title | Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions |
| title_full | Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions |
| title_fullStr | Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions |
| title_full_unstemmed | Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions |
| title_short | Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions |
| title_sort | multi level simulated fault injection for data dependent reliability analysis of rtl circuit descriptions |
| topic | digital circuits probabilistic circuits register transfer level reliability simulated fault injection |
| url | http://dx.doi.org/10.4316/AECE.2016.01013 |
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