Pre-Emphasis Pulse Design for Random-Access Memory
This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in th...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-06-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/12/1454 |
| _version_ | 1797529751569563648 |
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| author | Yoshihiro Sugiura Toru Tanzawa |
| author_facet | Yoshihiro Sugiura Toru Tanzawa |
| author_sort | Yoshihiro Sugiura |
| collection | DOAJ |
| description | This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time. |
| first_indexed | 2024-03-10T10:19:17Z |
| format | Article |
| id | doaj.art-2af69fd784ae444593e851bd7c234f4b |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T10:19:17Z |
| publishDate | 2021-06-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-2af69fd784ae444593e851bd7c234f4b2023-11-22T00:34:22ZengMDPI AGElectronics2079-92922021-06-011012145410.3390/electronics10121454Pre-Emphasis Pulse Design for Random-Access MemoryYoshihiro Sugiura0Toru Tanzawa1Faculty of Engineering, Shizuoka University, Hamamatsu 432-8561, JapanFaculty of Engineering, Shizuoka University, Hamamatsu 432-8561, JapanThis paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.https://www.mdpi.com/2079-9292/10/12/1454pre-emphasis pulserandom-access memoryRC delaybehavior model |
| spellingShingle | Yoshihiro Sugiura Toru Tanzawa Pre-Emphasis Pulse Design for Random-Access Memory Electronics pre-emphasis pulse random-access memory RC delay behavior model |
| title | Pre-Emphasis Pulse Design for Random-Access Memory |
| title_full | Pre-Emphasis Pulse Design for Random-Access Memory |
| title_fullStr | Pre-Emphasis Pulse Design for Random-Access Memory |
| title_full_unstemmed | Pre-Emphasis Pulse Design for Random-Access Memory |
| title_short | Pre-Emphasis Pulse Design for Random-Access Memory |
| title_sort | pre emphasis pulse design for random access memory |
| topic | pre-emphasis pulse random-access memory RC delay behavior model |
| url | https://www.mdpi.com/2079-9292/10/12/1454 |
| work_keys_str_mv | AT yoshihirosugiura preemphasispulsedesignforrandomaccessmemory AT torutanzawa preemphasispulsedesignforrandomaccessmemory |