A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT Devices
Modular multiplication is a crucial operation in public-key cryptography systems such as RSA and ECC. In this study, we analyze and improve the iteration steps of the classic Montgomery modular multiplication (MMM) algorithm and propose an interleaved pipeline (IP) structure, which meets the high-pe...
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| Format: | Article |
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MDPI AG
2023-07-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/12/15/3241 |
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| author | Hongshuo Li Shiwei Ren Weijiang Wang Jingqi Zhang Xiaohua Wang |
| author_facet | Hongshuo Li Shiwei Ren Weijiang Wang Jingqi Zhang Xiaohua Wang |
| author_sort | Hongshuo Li |
| collection | DOAJ |
| description | Modular multiplication is a crucial operation in public-key cryptography systems such as RSA and ECC. In this study, we analyze and improve the iteration steps of the classic Montgomery modular multiplication (MMM) algorithm and propose an interleaved pipeline (IP) structure, which meets the high-performance and low-cost requirements for Internet of Things devices. Compared to the classic pipeline structure, the IP does not require a multiplexing processing element (PE), which helps shorten the data path of intermediate results. We further introduce a disruption in the critical path to complete an iterative step of the MMM algorithm in two clock cycles. Our proposed hardware architecture is implemented on Xilinx Virtex-7 Series FPGA, using DSP48E1, to realize the multiplier. The implemented results show that the modular multiplication of 1024 bits by 2048 bits requires 1.03 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s and 2.13 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s, respectively. Moreover, our area–time–product analysis reveals a favorable outcome compared to the state-of-the-art designs across a 1024-bit and 2048-bit modulus. |
| first_indexed | 2024-03-11T00:29:09Z |
| format | Article |
| id | doaj.art-2afdbb99664646f3be8f9609de1fa4b9 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-11T00:29:09Z |
| publishDate | 2023-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-2afdbb99664646f3be8f9609de1fa4b92023-11-18T22:48:24ZengMDPI AGElectronics2079-92922023-07-011215324110.3390/electronics12153241A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT DevicesHongshuo Li0Shiwei Ren1Weijiang Wang2Jingqi Zhang3Xiaohua Wang4School of Integrated Circuits and Electronics, Beijing Institute of Technology (BIT), Beijing 100081, ChinaSchool of Integrated Circuits and Electronics, Beijing Institute of Technology (BIT), Beijing 100081, ChinaSchool of Integrated Circuits and Electronics, Beijing Institute of Technology (BIT), Beijing 100081, ChinaSchool of Integrated Circuits and Electronics, Beijing Institute of Technology (BIT), Beijing 100081, ChinaSchool of Integrated Circuits and Electronics, Beijing Institute of Technology (BIT), Beijing 100081, ChinaModular multiplication is a crucial operation in public-key cryptography systems such as RSA and ECC. In this study, we analyze and improve the iteration steps of the classic Montgomery modular multiplication (MMM) algorithm and propose an interleaved pipeline (IP) structure, which meets the high-performance and low-cost requirements for Internet of Things devices. Compared to the classic pipeline structure, the IP does not require a multiplexing processing element (PE), which helps shorten the data path of intermediate results. We further introduce a disruption in the critical path to complete an iterative step of the MMM algorithm in two clock cycles. Our proposed hardware architecture is implemented on Xilinx Virtex-7 Series FPGA, using DSP48E1, to realize the multiplier. The implemented results show that the modular multiplication of 1024 bits by 2048 bits requires 1.03 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s and 2.13 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s, respectively. Moreover, our area–time–product analysis reveals a favorable outcome compared to the state-of-the-art designs across a 1024-bit and 2048-bit modulus.https://www.mdpi.com/2079-9292/12/15/3241Montgomery modular multiplicationcryptosystemspipelinehigh performancelow costhardware implementation |
| spellingShingle | Hongshuo Li Shiwei Ren Weijiang Wang Jingqi Zhang Xiaohua Wang A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT Devices Electronics Montgomery modular multiplication cryptosystems pipeline high performance low cost hardware implementation |
| title | A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT Devices |
| title_full | A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT Devices |
| title_fullStr | A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT Devices |
| title_full_unstemmed | A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT Devices |
| title_short | A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT Devices |
| title_sort | low cost high performance montgomery modular multiplier based on pipeline interleaving for iot devices |
| topic | Montgomery modular multiplication cryptosystems pipeline high performance low cost hardware implementation |
| url | https://www.mdpi.com/2079-9292/12/15/3241 |
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