Comparación de las técnicas de extracción del voltaje de umbral basadas en la característica gm/ID del MOSFETs.
Context: In advanced ultralow-power devices, it is necessary to use the accuracy extraction procedures of the MOSFET threshold voltage to fully characterize the devices. These procedures are based in the measurement of the Tran-conductance efficiency (gm/ID) and its first derivative in function of t...
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| Format: | Article |
| Language: | Spanish |
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Universidad Distrital Francisco Jose de Caldas
2017-04-01
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| Series: | Tecnura |
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| Online Access: | http://revistas.udistrital.edu.co/ojs/index.php/Tecnura/article/view/9466 |
| _version_ | 1811339057096032256 |
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| author | Arturo Fajardo Jaimes |
| author_facet | Arturo Fajardo Jaimes |
| author_sort | Arturo Fajardo Jaimes |
| collection | DOAJ |
| description | Context: In advanced ultralow-power devices, it is necessary to use the accuracy extraction procedures of the MOSFET threshold voltage to fully characterize the devices. These procedures are based in the measurement of the Tran-conductance efficiency (gm/ID) and its first derivative in function of the voltage gate source (d(gm/ID)/dVGS). In order to increase their independency respect to the non-zero drain source voltage (VDS ≠0) it is used a process to correct the error. Theoretically, VDS should be 0 V; however, the VDS is grater than 10 mV in the experimental setup in order to avoid electrical noise, but less than a certain maximum value for allowing the MOSFET operation in the linear region of the weak inversion.
Objective: To compare the extraction procedure proposed by (MC Schneider et al., 2006) and the method proposed by (Rudenko et al., 2011) with a generic, controlled and coherent test scenario.
Method: This paper proposes a test scenario based on the Advanced Compact MOSFET model (ACM) of a long channel MOSFET made in a standard 0.35 mm CMOS process, implemented numerically in MATLABâ. The concept of Power Error Correction (PEC) was used to compare the two processes numerically; it quantifies the sensitivity of the extraction process to the effect by the non-zero voltage value of the VDS in the experimental setup (i.e., NZ-DS effect).
Results: The error correction procedure proposed by (Siebel et al., 2012, Schneider et al., 2006) estimates the NZ-DS effect better than the procedure proposed by (Rudenko et al., 2011), considering the average, maximum and minimum PEC obtained for both extraction methodologies for a long channel MOSFET fabricated in a standard CMOS process of 0.35 μm, when the VDS is less than 50 mV.
Conclusions: The Vth extraction procedure proposed by (MC Schneider et al., 2006) is more robust than the method proposed by (Rudenko et al., 2011) regarding the NZ-DS effect. |
| first_indexed | 2024-04-13T18:20:25Z |
| format | Article |
| id | doaj.art-2b68e67cd3254eeeaebef8c5994d2305 |
| institution | Directory Open Access Journal |
| issn | 2248-7638 0123-921X |
| language | Spanish |
| last_indexed | 2024-04-13T18:20:25Z |
| publishDate | 2017-04-01 |
| publisher | Universidad Distrital Francisco Jose de Caldas |
| record_format | Article |
| series | Tecnura |
| spelling | doaj.art-2b68e67cd3254eeeaebef8c5994d23052022-12-22T02:35:28ZspaUniversidad Distrital Francisco Jose de CaldasTecnura2248-76380123-921X2017-04-012152324410.14483/udistrital.jour.tecnura.2017.2.a028787Comparación de las técnicas de extracción del voltaje de umbral basadas en la característica gm/ID del MOSFETs.Arturo Fajardo Jaimes0Pontificia Universidad JaverianaContext: In advanced ultralow-power devices, it is necessary to use the accuracy extraction procedures of the MOSFET threshold voltage to fully characterize the devices. These procedures are based in the measurement of the Tran-conductance efficiency (gm/ID) and its first derivative in function of the voltage gate source (d(gm/ID)/dVGS). In order to increase their independency respect to the non-zero drain source voltage (VDS ≠0) it is used a process to correct the error. Theoretically, VDS should be 0 V; however, the VDS is grater than 10 mV in the experimental setup in order to avoid electrical noise, but less than a certain maximum value for allowing the MOSFET operation in the linear region of the weak inversion. Objective: To compare the extraction procedure proposed by (MC Schneider et al., 2006) and the method proposed by (Rudenko et al., 2011) with a generic, controlled and coherent test scenario. Method: This paper proposes a test scenario based on the Advanced Compact MOSFET model (ACM) of a long channel MOSFET made in a standard 0.35 mm CMOS process, implemented numerically in MATLABâ. The concept of Power Error Correction (PEC) was used to compare the two processes numerically; it quantifies the sensitivity of the extraction process to the effect by the non-zero voltage value of the VDS in the experimental setup (i.e., NZ-DS effect). Results: The error correction procedure proposed by (Siebel et al., 2012, Schneider et al., 2006) estimates the NZ-DS effect better than the procedure proposed by (Rudenko et al., 2011), considering the average, maximum and minimum PEC obtained for both extraction methodologies for a long channel MOSFET fabricated in a standard CMOS process of 0.35 μm, when the VDS is less than 50 mV. Conclusions: The Vth extraction procedure proposed by (MC Schneider et al., 2006) is more robust than the method proposed by (Rudenko et al., 2011) regarding the NZ-DS effect.http://revistas.udistrital.edu.co/ojs/index.php/Tecnura/article/view/9466Threshold voltage extraction, MOSFET modeling, Gm/ID transconductance efficiency |
| spellingShingle | Arturo Fajardo Jaimes Comparación de las técnicas de extracción del voltaje de umbral basadas en la característica gm/ID del MOSFETs. Tecnura Threshold voltage extraction, MOSFET modeling, Gm/ID transconductance efficiency |
| title | Comparación de las técnicas de extracción del voltaje de umbral basadas en la característica gm/ID del MOSFETs. |
| title_full | Comparación de las técnicas de extracción del voltaje de umbral basadas en la característica gm/ID del MOSFETs. |
| title_fullStr | Comparación de las técnicas de extracción del voltaje de umbral basadas en la característica gm/ID del MOSFETs. |
| title_full_unstemmed | Comparación de las técnicas de extracción del voltaje de umbral basadas en la característica gm/ID del MOSFETs. |
| title_short | Comparación de las técnicas de extracción del voltaje de umbral basadas en la característica gm/ID del MOSFETs. |
| title_sort | comparacion de las tecnicas de extraccion del voltaje de umbral basadas en la caracteristica gm id del mosfets |
| topic | Threshold voltage extraction, MOSFET modeling, Gm/ID transconductance efficiency |
| url | http://revistas.udistrital.edu.co/ojs/index.php/Tecnura/article/view/9466 |
| work_keys_str_mv | AT arturofajardojaimes comparaciondelastecnicasdeextracciondelvoltajedeumbralbasadasenlacaracteristicagmiddelmosfets |