IMPLEMENTATION OF A VERILOG-BASED DIGITAL RECEIVER FOR 2.4 GHz ZIGBEE APPLICATIONS ON FPGA
This paper presents the implementation of a digital receiver for 2.4 GHz Zigbee IEEE 802.15.4 applications on a Spartan3E XC3S500E field programmable gate array (FPGA). The proposed digital receiver comprises an offset quadrature phase shift keying (OQPSK) demodulator, chip synchronization, and a de...
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| Format: | Article |
| Language: | English |
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Taylor's University
2014-02-01
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| Series: | Journal of Engineering Science and Technology |
| Subjects: | |
| Online Access: | http://jestec.taylors.edu.my/Vol%209%20Issue%201%20February%2014/Volume%20(9)%20Issue%20(1)%20136-153.pdf |
| _version_ | 1828295037630283776 |
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| author | RAFIDAH AHMAD OTHMAN SIDEK SHUKRI KORAKKOTTIL KUNHI MOHD |
| author_facet | RAFIDAH AHMAD OTHMAN SIDEK SHUKRI KORAKKOTTIL KUNHI MOHD |
| author_sort | RAFIDAH AHMAD |
| collection | DOAJ |
| description | This paper presents the implementation of a digital receiver for 2.4 GHz Zigbee IEEE 802.15.4 applications on a Spartan3E XC3S500E field programmable gate array (FPGA). The proposed digital receiver comprises an offset quadrature phase shift keying (OQPSK) demodulator, chip synchronization, and a de-spreading
block. A new design method that uses Verilog hardware description language (HDL) code through Xilinx ISE version 12 was developed to design these blocks. These blocks were integrated into one top module for optimization. Simulation
and measurement were conducted to verify the functionality of the receiver. Implementation results show that the receiver design matched the theoretical expectation. The implementation configuration required up to 22% less slices, flip-flops (FFs), and look-up tables (LUTs) than that in previous research. The clock frequencies used were as low as 250 kHz and 2 MHz. |
| first_indexed | 2024-04-13T11:48:06Z |
| format | Article |
| id | doaj.art-2b7c0d4277d2429f8c8d71f385854d99 |
| institution | Directory Open Access Journal |
| issn | 1823-4690 |
| language | English |
| last_indexed | 2024-04-13T11:48:06Z |
| publishDate | 2014-02-01 |
| publisher | Taylor's University |
| record_format | Article |
| series | Journal of Engineering Science and Technology |
| spelling | doaj.art-2b7c0d4277d2429f8c8d71f385854d992022-12-22T02:48:08ZengTaylor's UniversityJournal of Engineering Science and Technology1823-46902014-02-0191136153IMPLEMENTATION OF A VERILOG-BASED DIGITAL RECEIVER FOR 2.4 GHz ZIGBEE APPLICATIONS ON FPGARAFIDAH AHMAD0OTHMAN SIDEK1SHUKRI KORAKKOTTIL KUNHI MOHD2Collaborative Microelectronic Design Excellence Centre (CEDEC), Universiti Sains Malaysia, Engineering Campus, 14300 Nibong Tebal, Seberang Perai Selatan, Penang, Malaysia Collaborative Microelectronic Design Excellence Centre (CEDEC), Universiti Sains Malaysia, Engineering Campus, 14300 Nibong Tebal, Seberang Perai Selatan, Penang, Malaysia Collaborative Microelectronic Design Excellence Centre (CEDEC), Universiti Sains Malaysia, Engineering Campus, 14300 Nibong Tebal, Seberang Perai Selatan, Penang, Malaysia This paper presents the implementation of a digital receiver for 2.4 GHz Zigbee IEEE 802.15.4 applications on a Spartan3E XC3S500E field programmable gate array (FPGA). The proposed digital receiver comprises an offset quadrature phase shift keying (OQPSK) demodulator, chip synchronization, and a de-spreading block. A new design method that uses Verilog hardware description language (HDL) code through Xilinx ISE version 12 was developed to design these blocks. These blocks were integrated into one top module for optimization. Simulation and measurement were conducted to verify the functionality of the receiver. Implementation results show that the receiver design matched the theoretical expectation. The implementation configuration required up to 22% less slices, flip-flops (FFs), and look-up tables (LUTs) than that in previous research. The clock frequencies used were as low as 250 kHz and 2 MHz.http://jestec.taylors.edu.my/Vol%209%20Issue%201%20February%2014/Volume%20(9)%20Issue%20(1)%20136-153.pdfVerilogDigital receiverZigbeeIEEE 802.15.4 standardFPGA |
| spellingShingle | RAFIDAH AHMAD OTHMAN SIDEK SHUKRI KORAKKOTTIL KUNHI MOHD IMPLEMENTATION OF A VERILOG-BASED DIGITAL RECEIVER FOR 2.4 GHz ZIGBEE APPLICATIONS ON FPGA Journal of Engineering Science and Technology Verilog Digital receiver Zigbee IEEE 802.15.4 standard FPGA |
| title | IMPLEMENTATION OF A VERILOG-BASED DIGITAL RECEIVER FOR 2.4 GHz ZIGBEE APPLICATIONS ON FPGA |
| title_full | IMPLEMENTATION OF A VERILOG-BASED DIGITAL RECEIVER FOR 2.4 GHz ZIGBEE APPLICATIONS ON FPGA |
| title_fullStr | IMPLEMENTATION OF A VERILOG-BASED DIGITAL RECEIVER FOR 2.4 GHz ZIGBEE APPLICATIONS ON FPGA |
| title_full_unstemmed | IMPLEMENTATION OF A VERILOG-BASED DIGITAL RECEIVER FOR 2.4 GHz ZIGBEE APPLICATIONS ON FPGA |
| title_short | IMPLEMENTATION OF A VERILOG-BASED DIGITAL RECEIVER FOR 2.4 GHz ZIGBEE APPLICATIONS ON FPGA |
| title_sort | implementation of a verilog based digital receiver for 2 4 ghz zigbee applications on fpga |
| topic | Verilog Digital receiver Zigbee IEEE 802.15.4 standard FPGA |
| url | http://jestec.taylors.edu.my/Vol%209%20Issue%201%20February%2014/Volume%20(9)%20Issue%20(1)%20136-153.pdf |
| work_keys_str_mv | AT rafidahahmad implementationofaverilogbaseddigitalreceiverfor24ghzzigbeeapplicationsonfpga AT othmansidek implementationofaverilogbaseddigitalreceiverfor24ghzzigbeeapplicationsonfpga AT shukrikorakkottilkunhimohd implementationofaverilogbaseddigitalreceiverfor24ghzzigbeeapplicationsonfpga |