FPGA-Oriented LDPC Decoder for Cyber-Physical Systems
A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (...
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MDPI AG
2020-05-01
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| Series: | Mathematics |
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| Online Access: | https://www.mdpi.com/2227-7390/8/5/723 |
| _version_ | 1797568797782048768 |
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| author | Mateusz Kuc Wojciech Sułek Dariusz Kania |
| author_facet | Mateusz Kuc Wojciech Sułek Dariusz Kania |
| author_sort | Mateusz Kuc |
| collection | DOAJ |
| description | A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems. |
| first_indexed | 2024-03-10T20:02:12Z |
| format | Article |
| id | doaj.art-2ba56a55c6464a6d8775caa8377a0c0b |
| institution | Directory Open Access Journal |
| issn | 2227-7390 |
| language | English |
| last_indexed | 2024-03-10T20:02:12Z |
| publishDate | 2020-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Mathematics |
| spelling | doaj.art-2ba56a55c6464a6d8775caa8377a0c0b2023-11-19T23:28:01ZengMDPI AGMathematics2227-73902020-05-018572310.3390/math8050723FPGA-Oriented LDPC Decoder for Cyber-Physical SystemsMateusz Kuc0Wojciech Sułek1Dariusz Kania2Institute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, PolandInstitute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, PolandInstitute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, PolandA potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.https://www.mdpi.com/2227-7390/8/5/723cyber physical systemsLDPCQC-LDPCFPGAmin-sumnormalized min-sum |
| spellingShingle | Mateusz Kuc Wojciech Sułek Dariusz Kania FPGA-Oriented LDPC Decoder for Cyber-Physical Systems Mathematics cyber physical systems LDPC QC-LDPC FPGA min-sum normalized min-sum |
| title | FPGA-Oriented LDPC Decoder for Cyber-Physical Systems |
| title_full | FPGA-Oriented LDPC Decoder for Cyber-Physical Systems |
| title_fullStr | FPGA-Oriented LDPC Decoder for Cyber-Physical Systems |
| title_full_unstemmed | FPGA-Oriented LDPC Decoder for Cyber-Physical Systems |
| title_short | FPGA-Oriented LDPC Decoder for Cyber-Physical Systems |
| title_sort | fpga oriented ldpc decoder for cyber physical systems |
| topic | cyber physical systems LDPC QC-LDPC FPGA min-sum normalized min-sum |
| url | https://www.mdpi.com/2227-7390/8/5/723 |
| work_keys_str_mv | AT mateuszkuc fpgaorientedldpcdecoderforcyberphysicalsystems AT wojciechsułek fpgaorientedldpcdecoderforcyberphysicalsystems AT dariuszkania fpgaorientedldpcdecoderforcyberphysicalsystems |