FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (...

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Bibliographic Details
Main Authors: Mateusz Kuc, Wojciech Sułek, Dariusz Kania
Format: Article
Language:English
Published: MDPI AG 2020-05-01
Series:Mathematics
Subjects:
cyber physical systems
LDPC
QC-LDPC
FPGA
min-sum
normalized min-sum
Online Access:https://www.mdpi.com/2227-7390/8/5/723

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