Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling
Abstract Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architectur...
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| Format: | Article |
| Language: | English |
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SpringerOpen
2021-10-01
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| Series: | EURASIP Journal on Wireless Communications and Networking |
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| Online Access: | https://doi.org/10.1186/s13638-021-02056-5 |
| _version_ | 1818581316802707456 |
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| author | Alireza Hasani Lukasz Lopacinski Rolf Kraemer |
| author_facet | Alireza Hasani Lukasz Lopacinski Rolf Kraemer |
| author_sort | Alireza Hasani |
| collection | DOAJ |
| description | Abstract Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of $$E_b/N_0$$ E b / N 0 until the BER of 1e−6. |
| first_indexed | 2024-12-16T07:31:34Z |
| format | Article |
| id | doaj.art-2bd3bfc712904125b964c52288fa6f66 |
| institution | Directory Open Access Journal |
| issn | 1687-1499 |
| language | English |
| last_indexed | 2024-12-16T07:31:34Z |
| publishDate | 2021-10-01 |
| publisher | SpringerOpen |
| record_format | Article |
| series | EURASIP Journal on Wireless Communications and Networking |
| spelling | doaj.art-2bd3bfc712904125b964c52288fa6f662022-12-21T22:39:20ZengSpringerOpenEURASIP Journal on Wireless Communications and Networking1687-14992021-10-012021111410.1186/s13638-021-02056-5Reduced-complexity decoding implementation of QC-LDPC codes with modified shufflingAlireza Hasani0Lukasz Lopacinski1Rolf Kraemer2IHP - Leibniz-Institut für innovative MikroelektronikIHP - Leibniz-Institut für innovative MikroelektronikIHP - Leibniz-Institut für innovative MikroelektronikAbstract Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of $$E_b/N_0$$ E b / N 0 until the BER of 1e−6.https://doi.org/10.1186/s13638-021-02056-5Quasi-cyclic low-density parity-check codeLayered decodingDecoding complexity |
| spellingShingle | Alireza Hasani Lukasz Lopacinski Rolf Kraemer Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling EURASIP Journal on Wireless Communications and Networking Quasi-cyclic low-density parity-check code Layered decoding Decoding complexity |
| title | Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling |
| title_full | Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling |
| title_fullStr | Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling |
| title_full_unstemmed | Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling |
| title_short | Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling |
| title_sort | reduced complexity decoding implementation of qc ldpc codes with modified shuffling |
| topic | Quasi-cyclic low-density parity-check code Layered decoding Decoding complexity |
| url | https://doi.org/10.1186/s13638-021-02056-5 |
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