Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms
Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great....
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-03-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/6/759 |
| _version_ | 1797540279552573440 |
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| author | Edel Díaz Raúl Mateos Emilio J. Bueno Rubén Nieto |
| author_facet | Edel Díaz Raúl Mateos Emilio J. Bueno Rubén Nieto |
| author_sort | Edel Díaz |
| collection | DOAJ |
| description | Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms. |
| first_indexed | 2024-03-10T12:57:50Z |
| format | Article |
| id | doaj.art-2c3b45a92965412ab91fb0e51f191f0a |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T12:57:50Z |
| publishDate | 2021-03-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-2c3b45a92965412ab91fb0e51f191f0a2023-11-21T11:43:54ZengMDPI AGElectronics2079-92922021-03-0110675910.3390/electronics10060759Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual PlatformsEdel Díaz0Raúl Mateos1Emilio J. Bueno2Rubén Nieto3Department of Electronics, University of Alcalá, 28801 Alcalá de Henares, SpainDepartment of Electronics, University of Alcalá, 28801 Alcalá de Henares, SpainDepartment of Electronics, University of Alcalá, 28801 Alcalá de Henares, SpainDepartment of Applied Mathematics, Materials Science and Engineering and Electronics Technology, Rey Juan Carlos University, 28933 Móstoles, Madrid, SpainPresently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.https://www.mdpi.com/2079-9292/10/6/759QEMUvirtual platformmulti-threadco-simulation hardware/software |
| spellingShingle | Edel Díaz Raúl Mateos Emilio J. Bueno Rubén Nieto Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms Electronics QEMU virtual platform multi-thread co-simulation hardware/software |
| title | Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms |
| title_full | Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms |
| title_fullStr | Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms |
| title_full_unstemmed | Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms |
| title_short | Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms |
| title_sort | enabling parallelized qemu for hardware software co simulation virtual platforms |
| topic | QEMU virtual platform multi-thread co-simulation hardware/software |
| url | https://www.mdpi.com/2079-9292/10/6/759 |
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