A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture
A test pattern generator generates a pseudorandom test pattern that can be weighted to reduce the fault coverage in a built-in self-test. The objective of this paper is to propose a new weighted TPG for a scan-based BIST architecture. The motivation of this work is to generate efficient weighted pat...
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9353528/ |
| _version_ | 1818921873157652480 |
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| author | Vishnupriya Shivakumar Chinnaiyan Senthilpari Zubaida Yusoff |
| author_facet | Vishnupriya Shivakumar Chinnaiyan Senthilpari Zubaida Yusoff |
| author_sort | Vishnupriya Shivakumar |
| collection | DOAJ |
| description | A test pattern generator generates a pseudorandom test pattern that can be weighted to reduce the fault coverage in a built-in self-test. The objective of this paper is to propose a new weighted TPG for a scan-based BIST architecture. The motivation of this work is to generate efficient weighted patterns for enabling scan chains with reduced power consumption and area. Additionally, the pseudo-primary seed of TPG is maximized to obtain a considerable length in the weighted pseudorandom patterns. The maximum-length weighted patterns are executed by assigning separate weights to the specific scan chains using a weight-enabled clock. This approach reduces the hardware overhead and achieves a low power consumption of 26.7 nW. Moreover, the proposed weighted TPG is applied in two different test-per-scan BIST architectures and achieves accurate results. The weighted patterns are also generated with fewer switching transitions and higher fault coverages of 98.81% and 97.35% in two different BIST architectures. This process is observed with six other circuits under test as their scan chains. The simulation results are tested with a SilTerra 0.13 μm process on the Mentor Graphics IC design platform. Furthermore, the proposed weighted TPG is enlarged to a higher bit TPG, which is compared to accomplish the performance strategies. The experimental results of the proposed TPG design are compared and tabulated with existing potential TPG designs. |
| first_indexed | 2024-12-20T01:44:33Z |
| format | Article |
| id | doaj.art-2c9285be1e6d41b787ca2fe3156380d0 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-20T01:44:33Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-2c9285be1e6d41b787ca2fe3156380d02022-12-21T19:57:48ZengIEEEIEEE Access2169-35362021-01-019293662937910.1109/ACCESS.2021.30591719353528A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test ArchitectureVishnupriya Shivakumar0https://orcid.org/0000-0003-0804-7957Chinnaiyan Senthilpari1https://orcid.org/0000-0002-3775-5621Zubaida Yusoff2Faculty of Engineering, Multimedia University, Cyberjaya, MalaysiaFaculty of Engineering, Multimedia University, Cyberjaya, MalaysiaFaculty of Engineering, Multimedia University, Cyberjaya, MalaysiaA test pattern generator generates a pseudorandom test pattern that can be weighted to reduce the fault coverage in a built-in self-test. The objective of this paper is to propose a new weighted TPG for a scan-based BIST architecture. The motivation of this work is to generate efficient weighted patterns for enabling scan chains with reduced power consumption and area. Additionally, the pseudo-primary seed of TPG is maximized to obtain a considerable length in the weighted pseudorandom patterns. The maximum-length weighted patterns are executed by assigning separate weights to the specific scan chains using a weight-enabled clock. This approach reduces the hardware overhead and achieves a low power consumption of 26.7 nW. Moreover, the proposed weighted TPG is applied in two different test-per-scan BIST architectures and achieves accurate results. The weighted patterns are also generated with fewer switching transitions and higher fault coverages of 98.81% and 97.35% in two different BIST architectures. This process is observed with six other circuits under test as their scan chains. The simulation results are tested with a SilTerra 0.13 μm process on the Mentor Graphics IC design platform. Furthermore, the proposed weighted TPG is enlarged to a higher bit TPG, which is compared to accomplish the performance strategies. The experimental results of the proposed TPG design are compared and tabulated with existing potential TPG designs.https://ieeexplore.ieee.org/document/9353528/Built-in self-test (BIST)circuit under test (CUT)test-pattern generator (TPG) |
| spellingShingle | Vishnupriya Shivakumar Chinnaiyan Senthilpari Zubaida Yusoff A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture IEEE Access Built-in self-test (BIST) circuit under test (CUT) test-pattern generator (TPG) |
| title | A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture |
| title_full | A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture |
| title_fullStr | A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture |
| title_full_unstemmed | A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture |
| title_short | A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture |
| title_sort | low power and area efficient design of a weighted pseudorandom test pattern generator for a test per scan built in self test architecture |
| topic | Built-in self-test (BIST) circuit under test (CUT) test-pattern generator (TPG) |
| url | https://ieeexplore.ieee.org/document/9353528/ |
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