The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process

<p>Abstract</p> <p>Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are me...

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Bibliographic Details
Main Authors: Choi Sung-Jin, Jang Moongyu, Park Youngsam, Jun Myungsim, Hyun Younghoon, Zyung Taehyoung
Format: Article
Language:English
Published: SpringerOpen 2010-01-01
Series:Nanoscale Research Letters
Subjects:
Online Access:http://dx.doi.org/10.1007/s11671-010-9690-2
Description
Summary:<p>Abstract</p> <p>Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 &#956;V/K for p-leg and &#8722;94 &#956;V/K for n-leg. The maximum attainable power factor is 0.74 mW/m K<sup>2</sup> at room temperature.</p>
ISSN:1931-7573
1556-276X