A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems
Abstract In today's communication systems, it has become prominent for processing elements (PEs) to receive requests with simultaneous, conflicting signals, which are unpredicted and randomly triggered. In such a case, multiple overlapping signal requests can potentially compete in the same PE...
Main Authors: | Saleh Abdelhafeez, Shadi M. S. Harb |
---|---|
Format: | Article |
Language: | English |
Published: |
Hindawi-IET
2023-07-01
|
Series: | IET Computers & Digital Techniques |
Subjects: | |
Online Access: | https://doi.org/10.1049/cdt2.12059 |
Similar Items
-
DISEÑO DE UN AMPLIFICADOR RIEL A RIEL CON TECNOLOGÍA CMOS 0,18 µm DESENHO DE UM AMPLIFICADOR DO TRILHO-A-TRILHO COM TECNOLOGIA CMOS 0,18 µm DESIGN OF A RAIL-TO-RAIL AMPLIFIER WITH 0.18 µm TECHNOLOGY
by: Diego F. Hernández, et al.
Published: (2012-06-01) -
Logical gates recognition in a flat transistor circuit
by: D. I. Cheremisinov, et al.
Published: (2021-12-01) -
Design and Study the Performance of a CMOS-Based Ring Oscillator Architecture for 5G Mobile Communication
by: Abdul Rahman, et al.
Published: (2024-02-01) -
An adjustable 0.3 V current winner‐take‐all circuit for analogue neural networks
by: Meysam Akbari, et al.
Published: (2021-08-01) -
Antenna-on-Chip for Millimeter Wave Applications Using CMOS Process Technology
by: Ming-An Chung, et al.
Published: (2023-02-01)