Algorithm and VLSI Architecture of a Near-Optimum Symbol Detector for QSM MIMO Systems
Driven by the rapidly growing demand for high quality of service (QoS) in wireless communications, quadrature spatial modulation (QSM) multiple-input multiple-output (MIMO) technologies have received intensive research attention. In this paper, a multiplier-free and divider-free detection algorithm...
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IEEE
2023-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10363193/ |
| _version_ | 1827398941969219584 |
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| author | Mao-Hsu Yen Hoang-Yang Lu Ken-Hua Lu Shao-Yueh Lin Chia-Chen Chan |
| author_facet | Mao-Hsu Yen Hoang-Yang Lu Ken-Hua Lu Shao-Yueh Lin Chia-Chen Chan |
| author_sort | Mao-Hsu Yen |
| collection | DOAJ |
| description | Driven by the rapidly growing demand for high quality of service (QoS) in wireless communications, quadrature spatial modulation (QSM) multiple-input multiple-output (MIMO) technologies have received intensive research attention. In this paper, a multiplier-free and divider-free detection algorithm and a corresponding hardware architecture are presented. The proposed algorithm has four steps: 1) applying COordinate Rotation DIgital Computer (CORDIC)-based Givens rotations to QR decompose the fading channel matrices, 2) mapping the transmitted M-ary quadrature amplitude modulation (M-QAM) symbols to the binary phase shift keying (BPSK)-modulated bits, 3) symbol slicing to estimate the transmitted symbols for all transmit antenna combinations (TACs), and 4) measuring the likelihood distances and finding the final solution. Based on hardware considerations for high-speed processing, no multipliers or dividers are used in the four corresponding hardware modules. Finally, computer simulations and hardware implementation are conducted for a configuration with four transmit antennas, two active transmit antennas, and four receive antennas. According to the simulation results, the proposed algorithm performs almost as well as the optimal method but has a lower computational complexity. Furthermore, according to the hardware implementation results, the proposed architecture needs 547k gates (kGEs), has a preprocessing latency of 64 clock cycles, provides a throughput rate of 1 Gbps and has a hardware efficiency of 1.83 (Mbps/kGEs) when operating at a frequency of 500 MHz. The above results also show that even for fast fading channels, the proposed detector is still a promising candidate for providing a high throughput rate and an acceptable bit error rate (BER). |
| first_indexed | 2024-03-08T19:37:06Z |
| format | Article |
| id | doaj.art-2f62c66ea4fd4f8591e3d50a8b0cfe99 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-03-08T19:37:06Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-2f62c66ea4fd4f8591e3d50a8b0cfe992023-12-26T00:07:01ZengIEEEIEEE Access2169-35362023-01-011114411314412510.1109/ACCESS.2023.334383810363193Algorithm and VLSI Architecture of a Near-Optimum Symbol Detector for QSM MIMO SystemsMao-Hsu Yen0https://orcid.org/0000-0001-9195-4173Hoang-Yang Lu1https://orcid.org/0000-0002-9831-7588Ken-Hua Lu2https://orcid.org/0009-0001-2231-5068Shao-Yueh Lin3https://orcid.org/0009-0005-3614-3702Chia-Chen Chan4https://orcid.org/0009-0005-5040-8957Department of Computer Science and Information Engineering, National Taiwan Ocean University, Keelung, TaiwanDepartment of Electrical Engineering, National Taiwan Ocean University, Keelung, TaiwanDepartment of Computer Science and Information Engineering, National Taiwan Ocean University, Keelung, TaiwanDepartment of Computer Science and Information Engineering, National Taiwan Ocean University, Keelung, TaiwanDepartment of Electrical Engineering, National Taiwan Ocean University, Keelung, TaiwanDriven by the rapidly growing demand for high quality of service (QoS) in wireless communications, quadrature spatial modulation (QSM) multiple-input multiple-output (MIMO) technologies have received intensive research attention. In this paper, a multiplier-free and divider-free detection algorithm and a corresponding hardware architecture are presented. The proposed algorithm has four steps: 1) applying COordinate Rotation DIgital Computer (CORDIC)-based Givens rotations to QR decompose the fading channel matrices, 2) mapping the transmitted M-ary quadrature amplitude modulation (M-QAM) symbols to the binary phase shift keying (BPSK)-modulated bits, 3) symbol slicing to estimate the transmitted symbols for all transmit antenna combinations (TACs), and 4) measuring the likelihood distances and finding the final solution. Based on hardware considerations for high-speed processing, no multipliers or dividers are used in the four corresponding hardware modules. Finally, computer simulations and hardware implementation are conducted for a configuration with four transmit antennas, two active transmit antennas, and four receive antennas. According to the simulation results, the proposed algorithm performs almost as well as the optimal method but has a lower computational complexity. Furthermore, according to the hardware implementation results, the proposed architecture needs 547k gates (kGEs), has a preprocessing latency of 64 clock cycles, provides a throughput rate of 1 Gbps and has a hardware efficiency of 1.83 (Mbps/kGEs) when operating at a frequency of 500 MHz. The above results also show that even for fast fading channels, the proposed detector is still a promising candidate for providing a high throughput rate and an acceptable bit error rate (BER).https://ieeexplore.ieee.org/document/10363193/Quadrature spatial modulationgivens rotationcoordinate rotation digital computer (CORDIC) |
| spellingShingle | Mao-Hsu Yen Hoang-Yang Lu Ken-Hua Lu Shao-Yueh Lin Chia-Chen Chan Algorithm and VLSI Architecture of a Near-Optimum Symbol Detector for QSM MIMO Systems IEEE Access Quadrature spatial modulation givens rotation coordinate rotation digital computer (CORDIC) |
| title | Algorithm and VLSI Architecture of a Near-Optimum Symbol Detector for QSM MIMO Systems |
| title_full | Algorithm and VLSI Architecture of a Near-Optimum Symbol Detector for QSM MIMO Systems |
| title_fullStr | Algorithm and VLSI Architecture of a Near-Optimum Symbol Detector for QSM MIMO Systems |
| title_full_unstemmed | Algorithm and VLSI Architecture of a Near-Optimum Symbol Detector for QSM MIMO Systems |
| title_short | Algorithm and VLSI Architecture of a Near-Optimum Symbol Detector for QSM MIMO Systems |
| title_sort | algorithm and vlsi architecture of a near optimum symbol detector for qsm mimo systems |
| topic | Quadrature spatial modulation givens rotation coordinate rotation digital computer (CORDIC) |
| url | https://ieeexplore.ieee.org/document/10363193/ |
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