FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision
In this paper, we propose an FPGA-based enhanced-SIFT with feature matching for stereo vision. Gaussian blur and difference of Gaussian pyramids are realized in parallel to accelerate the processing time required for multiple convolutions. As for the feature descriptor, a simple triangular identific...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-07-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/14/1632 |
| _version_ | 1797527293538598912 |
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| author | Chien-Hung Kuo Erh-Hsu Huang Chiang-Heng Chien Chen-Chien Hsu |
| author_facet | Chien-Hung Kuo Erh-Hsu Huang Chiang-Heng Chien Chen-Chien Hsu |
| author_sort | Chien-Hung Kuo |
| collection | DOAJ |
| description | In this paper, we propose an FPGA-based enhanced-SIFT with feature matching for stereo vision. Gaussian blur and difference of Gaussian pyramids are realized in parallel to accelerate the processing time required for multiple convolutions. As for the feature descriptor, a simple triangular identification approach with a look-up table is proposed to efficiently determine the direction and gradient of the feature points. Thus, the dimension of the feature descriptor in this paper is reduced by half compared to conventional approaches. As far as feature detection is concerned, the condition for high-contrast detection is simplified by moderately changing a threshold value, which also benefits the reduction of the resulting hardware in realization. The proposed enhanced-SIFT not only accelerates the operational speed but also reduces the hardware cost. The experiment results show that the proposed enhanced-SIFT reaches a frame rate of 205 fps for 640 × 480 images. Integrated with two enhanced-SIFT, a finite-area parallel checking is also proposed without the aid of external memory to improve the efficiency of feature matching. The resulting frame rate by the proposed stereo vision matching can be as high as 181 fps with good matching accuracy as demonstrated in the experimental results. |
| first_indexed | 2024-03-10T09:40:54Z |
| format | Article |
| id | doaj.art-2f9262e6ffc04ef4ac3a29e8273f3335 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T09:40:54Z |
| publishDate | 2021-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-2f9262e6ffc04ef4ac3a29e8273f33352023-11-22T03:37:33ZengMDPI AGElectronics2079-92922021-07-011014163210.3390/electronics10141632FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo VisionChien-Hung Kuo0Erh-Hsu Huang1Chiang-Heng Chien2Chen-Chien Hsu3Department of Electrical Engineering, National Taiwan Normal University, Taipei 10610, TaiwanDepartment of Electrical Engineering, National Taiwan Normal University, Taipei 10610, TaiwanDepartment of Electrical Engineering, National Taiwan Normal University, Taipei 10610, TaiwanDepartment of Electrical Engineering, National Taiwan Normal University, Taipei 10610, TaiwanIn this paper, we propose an FPGA-based enhanced-SIFT with feature matching for stereo vision. Gaussian blur and difference of Gaussian pyramids are realized in parallel to accelerate the processing time required for multiple convolutions. As for the feature descriptor, a simple triangular identification approach with a look-up table is proposed to efficiently determine the direction and gradient of the feature points. Thus, the dimension of the feature descriptor in this paper is reduced by half compared to conventional approaches. As far as feature detection is concerned, the condition for high-contrast detection is simplified by moderately changing a threshold value, which also benefits the reduction of the resulting hardware in realization. The proposed enhanced-SIFT not only accelerates the operational speed but also reduces the hardware cost. The experiment results show that the proposed enhanced-SIFT reaches a frame rate of 205 fps for 640 × 480 images. Integrated with two enhanced-SIFT, a finite-area parallel checking is also proposed without the aid of external memory to improve the efficiency of feature matching. The resulting frame rate by the proposed stereo vision matching can be as high as 181 fps with good matching accuracy as demonstrated in the experimental results.https://www.mdpi.com/2079-9292/10/14/1632SIFTFPGAfeature detectionfeature descriptorfeature matchingstereo vision |
| spellingShingle | Chien-Hung Kuo Erh-Hsu Huang Chiang-Heng Chien Chen-Chien Hsu FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision Electronics SIFT FPGA feature detection feature descriptor feature matching stereo vision |
| title | FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision |
| title_full | FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision |
| title_fullStr | FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision |
| title_full_unstemmed | FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision |
| title_short | FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision |
| title_sort | fpga design of enhanced scale invariant feature transform with finite area parallel feature matching for stereo vision |
| topic | SIFT FPGA feature detection feature descriptor feature matching stereo vision |
| url | https://www.mdpi.com/2079-9292/10/14/1632 |
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