FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision

FPGA Design of Enhanced Scale-Invariant Feature Transform with Finite-Area Parallel Feature Matching for Stereo Vision

In this paper, we propose an FPGA-based enhanced-SIFT with feature matching for stereo vision. Gaussian blur and difference of Gaussian pyramids are realized in parallel to accelerate the processing time required for multiple convolutions. As for the feature descriptor, a simple triangular identific...

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Bibliographic Details
Main Authors: Chien-Hung Kuo, Erh-Hsu Huang, Chiang-Heng Chien, Chen-Chien Hsu
Format: Article
Language:English
Published: MDPI AG 2021-07-01
Series:Electronics
Subjects:
SIFT
FPGA
feature detection
feature descriptor
feature matching
stereo vision
Online Access:https://www.mdpi.com/2079-9292/10/14/1632

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