Design Considerations for Integrated Radar Chirp Synthesizers
Phase-locked loops (PLLs) effectively generate frequency chirps for frequency-modulated continuous-wave (FMCW) radar and are ideal for integrated circuit implementations. This paper discusses the design requirements for integrated PLLs used as chirp synthesizers for FMCW radar and focuses on an anal...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2019-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/8618322/ |
| _version_ | 1818855310919467008 |
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| author | Daniel Weyer Mehmet Batuhan Dayanik Lu Jie Ahmed Albalawi Abdulhamed Alothaimen Mohammed Aseeri Michael P. Flynn |
| author_facet | Daniel Weyer Mehmet Batuhan Dayanik Lu Jie Ahmed Albalawi Abdulhamed Alothaimen Mohammed Aseeri Michael P. Flynn |
| author_sort | Daniel Weyer |
| collection | DOAJ |
| description | Phase-locked loops (PLLs) effectively generate frequency chirps for frequency-modulated continuous-wave (FMCW) radar and are ideal for integrated circuit implementations. This paper discusses the design requirements for integrated PLLs used as chirp synthesizers for FMCW radar and focuses on an analysis of the radar performance based on the PLL configuration. The fundamental principles of the FMCW radar are reviewed, and the importance of low synthesizer phase noise for reliable target detection is quantified. This paper provides guidance for the design of chirp synthesizer PLLs by analyzing the impact of the PLL configuration on the accuracy and reliability of the radar. The presented analysis approach allows for a straightforward study of the radar performance and quantifies the optimal settings of a PLL-based chirp synthesizer for a given application scenario, while the developed methodology can be easily applied to other scenarios. A novel digital chirp synthesizer PLL design that meets the requirements of FMCW radar is presented. The synthesizer prototype fabricated in 65-nm CMOS drives a radar testbed to verify the effectiveness of the synthesizer design in a complete FMCW radar system. |
| first_indexed | 2024-12-19T08:06:35Z |
| format | Article |
| id | doaj.art-2fe13378197c440e92e7eacbcab8c3f5 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-19T08:06:35Z |
| publishDate | 2019-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-2fe13378197c440e92e7eacbcab8c3f52022-12-21T20:29:44ZengIEEEIEEE Access2169-35362019-01-017137231373610.1109/ACCESS.2019.28933138618322Design Considerations for Integrated Radar Chirp SynthesizersDaniel Weyer0https://orcid.org/0000-0002-8355-9402Mehmet Batuhan Dayanik1Lu Jie2Ahmed Albalawi3Abdulhamed Alothaimen4Mohammed Aseeri5Michael P. Flynn6Silicon Laboratories Inc., Austin, TX, USABroadcom Ltd., Irvine, CA, USADepartment of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USAKing Abdulaziz City for Science and Technology, Riyadh, Saudi ArabiaKing Abdulaziz City for Science and Technology, Riyadh, Saudi ArabiaKing Abdulaziz City for Science and Technology, Riyadh, Saudi ArabiaDepartment of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USAPhase-locked loops (PLLs) effectively generate frequency chirps for frequency-modulated continuous-wave (FMCW) radar and are ideal for integrated circuit implementations. This paper discusses the design requirements for integrated PLLs used as chirp synthesizers for FMCW radar and focuses on an analysis of the radar performance based on the PLL configuration. The fundamental principles of the FMCW radar are reviewed, and the importance of low synthesizer phase noise for reliable target detection is quantified. This paper provides guidance for the design of chirp synthesizer PLLs by analyzing the impact of the PLL configuration on the accuracy and reliability of the radar. The presented analysis approach allows for a straightforward study of the radar performance and quantifies the optimal settings of a PLL-based chirp synthesizer for a given application scenario, while the developed methodology can be easily applied to other scenarios. A novel digital chirp synthesizer PLL design that meets the requirements of FMCW radar is presented. The synthesizer prototype fabricated in 65-nm CMOS drives a radar testbed to verify the effectiveness of the synthesizer design in a complete FMCW radar system.https://ieeexplore.ieee.org/document/8618322/Chirp linearitychirp synthesisfrequency-modulated continuous-wave (FMCW) radarfully-integrated chirp synthesizerphase locked loop (PLL)phase noise |
| spellingShingle | Daniel Weyer Mehmet Batuhan Dayanik Lu Jie Ahmed Albalawi Abdulhamed Alothaimen Mohammed Aseeri Michael P. Flynn Design Considerations for Integrated Radar Chirp Synthesizers IEEE Access Chirp linearity chirp synthesis frequency-modulated continuous-wave (FMCW) radar fully-integrated chirp synthesizer phase locked loop (PLL) phase noise |
| title | Design Considerations for Integrated Radar Chirp Synthesizers |
| title_full | Design Considerations for Integrated Radar Chirp Synthesizers |
| title_fullStr | Design Considerations for Integrated Radar Chirp Synthesizers |
| title_full_unstemmed | Design Considerations for Integrated Radar Chirp Synthesizers |
| title_short | Design Considerations for Integrated Radar Chirp Synthesizers |
| title_sort | design considerations for integrated radar chirp synthesizers |
| topic | Chirp linearity chirp synthesis frequency-modulated continuous-wave (FMCW) radar fully-integrated chirp synthesizer phase locked loop (PLL) phase noise |
| url | https://ieeexplore.ieee.org/document/8618322/ |
| work_keys_str_mv | AT danielweyer designconsiderationsforintegratedradarchirpsynthesizers AT mehmetbatuhandayanik designconsiderationsforintegratedradarchirpsynthesizers AT lujie designconsiderationsforintegratedradarchirpsynthesizers AT ahmedalbalawi designconsiderationsforintegratedradarchirpsynthesizers AT abdulhamedalothaimen designconsiderationsforintegratedradarchirpsynthesizers AT mohammedaseeri designconsiderationsforintegratedradarchirpsynthesizers AT michaelpflynn designconsiderationsforintegratedradarchirpsynthesizers |