Design Considerations for Integrated Radar Chirp Synthesizers

Design Considerations for Integrated Radar Chirp Synthesizers

Phase-locked loops (PLLs) effectively generate frequency chirps for frequency-modulated continuous-wave (FMCW) radar and are ideal for integrated circuit implementations. This paper discusses the design requirements for integrated PLLs used as chirp synthesizers for FMCW radar and focuses on an anal...

Full description

Bibliographic Details
Main Authors: Daniel Weyer, Mehmet Batuhan Dayanik, Lu Jie, Ahmed Albalawi, Abdulhamed Alothaimen, Mohammed Aseeri, Michael P. Flynn
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Chirp linearity
chirp synthesis
frequency-modulated continuous-wave (FMCW) radar
fully-integrated chirp synthesizer
phase locked loop (PLL)
phase noise
Online Access:https://ieeexplore.ieee.org/document/8618322/

Internet

https://ieeexplore.ieee.org/document/8618322/

Similar Items