Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect
Networks-on-Chip (NoCs) have become the <i>de-facto</i> on-chip interconnect for multi/manycore systems. A typical NoC router is made up of buffers used to store packets that are unable to advance to their desired destination. However, buffers consume significant power/area and are often...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-12-01
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| Series: | Micromachines |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2072-666X/13/12/2246 |
| _version_ | 1797456203292344320 |
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| author | Charles Effiong Gilles Sassatelli Abdoulaye Gamatié |
| author_facet | Charles Effiong Gilles Sassatelli Abdoulaye Gamatié |
| author_sort | Charles Effiong |
| collection | DOAJ |
| description | Networks-on-Chip (NoCs) have become the <i>de-facto</i> on-chip interconnect for multi/manycore systems. A typical NoC router is made up of buffers used to store packets that are unable to advance to their desired destination. However, buffers consume significant power/area and are often underutilized, especially in cases of applications with non-uniform traffic patterns thus leading to performance degradation for such applications. To improve network performance, the Roundabout NoC (<i>R-NoC</i>) concept is considered. <i>R-NoC</i> is inspired by real-life multi-lane traffic roundabouts and consists of lanes that are shared by multiple input/output ports to maximize buffering resource utilization. <i>R-NoC</i> relies on router-internal adaptive routing that decides the lane path based on back pressure. Back pressure makes it possible to assess lane utilization and route packets accordingly. This is made possible thanks to the use of elastic buffers for control flow, a clever type of handshaking in a way similar to asynchronous circuits. Another prominent feature of R-NoC is that internal routing and arbitration are completely distributed which allows for significant freedom in deciding internal router topology and parameters. This work leverages this property and proposes novel yet unexplored configurations for which an in-depth evaluation of corresponding implementations on 45 nm CMOS technology is given. Each configuration is evaluated performance and power-wise on both synthetic and real application traffic. Several <i>R-NoC</i> configurations are identified and demonstrated to provide very significant performance improvements over standard mesh configurations and a typical input-buffered router, without compromising area and power consumption. Exploiting the distributed nature of <i>R-NoC</i> routers, a diagonally-linked configuration is then proposed which incurs moderate area overhead and features yet better performance and energy efficiency. |
| first_indexed | 2024-03-09T16:04:56Z |
| format | Article |
| id | doaj.art-30d2afba2acd4220832885710a7ff5c0 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-09T16:04:56Z |
| publishDate | 2022-12-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-30d2afba2acd4220832885710a7ff5c02023-11-24T16:46:41ZengMDPI AGMicromachines2072-666X2022-12-011312224610.3390/mi13122246Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance InterconnectCharles Effiong0Gilles Sassatelli1Abdoulaye Gamatié2LIRMM, University of Montpellier, CNRS, 34000 Montpellier, FranceLIRMM, University of Montpellier, CNRS, 34000 Montpellier, FranceLIRMM, University of Montpellier, CNRS, 34000 Montpellier, FranceNetworks-on-Chip (NoCs) have become the <i>de-facto</i> on-chip interconnect for multi/manycore systems. A typical NoC router is made up of buffers used to store packets that are unable to advance to their desired destination. However, buffers consume significant power/area and are often underutilized, especially in cases of applications with non-uniform traffic patterns thus leading to performance degradation for such applications. To improve network performance, the Roundabout NoC (<i>R-NoC</i>) concept is considered. <i>R-NoC</i> is inspired by real-life multi-lane traffic roundabouts and consists of lanes that are shared by multiple input/output ports to maximize buffering resource utilization. <i>R-NoC</i> relies on router-internal adaptive routing that decides the lane path based on back pressure. Back pressure makes it possible to assess lane utilization and route packets accordingly. This is made possible thanks to the use of elastic buffers for control flow, a clever type of handshaking in a way similar to asynchronous circuits. Another prominent feature of R-NoC is that internal routing and arbitration are completely distributed which allows for significant freedom in deciding internal router topology and parameters. This work leverages this property and proposes novel yet unexplored configurations for which an in-depth evaluation of corresponding implementations on 45 nm CMOS technology is given. Each configuration is evaluated performance and power-wise on both synthetic and real application traffic. Several <i>R-NoC</i> configurations are identified and demonstrated to provide very significant performance improvements over standard mesh configurations and a typical input-buffered router, without compromising area and power consumption. Exploiting the distributed nature of <i>R-NoC</i> routers, a diagonally-linked configuration is then proposed which incurs moderate area overhead and features yet better performance and energy efficiency.https://www.mdpi.com/2072-666X/13/12/2246network-on-chipbuffersresource sharingenergy efficiencyadaptive control |
| spellingShingle | Charles Effiong Gilles Sassatelli Abdoulaye Gamatié Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect Micromachines network-on-chip buffers resource sharing energy efficiency adaptive control |
| title | Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect |
| title_full | Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect |
| title_fullStr | Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect |
| title_full_unstemmed | Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect |
| title_short | Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect |
| title_sort | combined distributed shared buffered and diagonally linked mesh topology for high performance interconnect |
| topic | network-on-chip buffers resource sharing energy efficiency adaptive control |
| url | https://www.mdpi.com/2072-666X/13/12/2246 |
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