Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect
Networks-on-Chip (NoCs) have become the <i>de-facto</i> on-chip interconnect for multi/manycore systems. A typical NoC router is made up of buffers used to store packets that are unable to advance to their desired destination. However, buffers consume significant power/area and are often...
| Glavni autori: | , , |
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| Format: | Članak |
| Jezik: | English |
| Izdano: |
MDPI AG
2022-12-01
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| Serija: | Micromachines |
| Teme: | |
| Online pristup: | https://www.mdpi.com/2072-666X/13/12/2246 |