A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers
This paper analyzes the performance requirements that need to be met by a clock generator applied to a low-temperature quantum computer and analyzes the negative effects on the clock generator circuit under low-temperature conditions. In order to meet the performance requirements proposed in this pa...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-07-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/12/15/3237 |
| _version_ | 1797586862024425472 |
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| author | Kewei Xin Mingche Lai Fangxu Lv Kaile Guo Zhengbin Pang Chaolong Xu Geng Zhang Wenchen Wang Meng Li |
| author_facet | Kewei Xin Mingche Lai Fangxu Lv Kaile Guo Zhengbin Pang Chaolong Xu Geng Zhang Wenchen Wang Meng Li |
| author_sort | Kewei Xin |
| collection | DOAJ |
| description | This paper analyzes the performance requirements that need to be met by a clock generator applied to a low-temperature quantum computer and analyzes the negative effects on the clock generator circuit under low-temperature conditions. In order to meet the performance requirements proposed in this paper and suppress the negative effects brought about by the low temperature, a clock generator for ultra-low-temperature quantum computing is designed. This clock generator is designed by using F-CLASS Voltage Controlled Oscillator (VCO), power filter, tail resistor, differential charge pump, and other techniques. And the noise characteristics of the clock generator are analyzed by Impulse Sensitive Function (ISF) and simulation results. After simulation tests, the average power consumption of the clock generator designed in this paper is 7 mW, the phase noise is −121 dBc/Hz@1 MHz, and the jitter is 62 fs. The performance of the clock generator meets the performance requirements proposed in this paper, and the reduction in the corner frequency proves that the circuit will have better performance at low temperatures. |
| first_indexed | 2024-03-11T00:29:10Z |
| format | Article |
| id | doaj.art-31ff3353e22641f380b40f3f381a816c |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-11T00:29:10Z |
| publishDate | 2023-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-31ff3353e22641f380b40f3f381a816c2023-11-18T22:48:20ZengMDPI AGElectronics2079-92922023-07-011215323710.3390/electronics12153237A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum ComputersKewei Xin0Mingche Lai1Fangxu Lv2Kaile Guo3Zhengbin Pang4Chaolong Xu5Geng Zhang6Wenchen Wang7Meng Li8College of Computer Science and Technology, National University of Defense Technology, Changsha 410000, ChinaCollege of Computer Science and Technology, National University of Defense Technology, Changsha 410000, ChinaCollege of Computer Science and Technology, National University of Defense Technology, Changsha 410000, ChinaCollege of Computer Science and Technology, National University of Defense Technology, Changsha 410000, ChinaCollege of Computer Science and Technology, National University of Defense Technology, Changsha 410000, ChinaCollege of Computer Science and Technology, National University of Defense Technology, Changsha 410000, ChinaCollege of Computer Science and Technology, National University of Defense Technology, Changsha 410000, ChinaCollege of Computer Science and Technology, National University of Defense Technology, Changsha 410000, ChinaCollege of Computer Science and Technology, National University of Defense Technology, Changsha 410000, ChinaThis paper analyzes the performance requirements that need to be met by a clock generator applied to a low-temperature quantum computer and analyzes the negative effects on the clock generator circuit under low-temperature conditions. In order to meet the performance requirements proposed in this paper and suppress the negative effects brought about by the low temperature, a clock generator for ultra-low-temperature quantum computing is designed. This clock generator is designed by using F-CLASS Voltage Controlled Oscillator (VCO), power filter, tail resistor, differential charge pump, and other techniques. And the noise characteristics of the clock generator are analyzed by Impulse Sensitive Function (ISF) and simulation results. After simulation tests, the average power consumption of the clock generator designed in this paper is 7 mW, the phase noise is −121 dBc/Hz@1 MHz, and the jitter is 62 fs. The performance of the clock generator meets the performance requirements proposed in this paper, and the reduction in the corner frequency proves that the circuit will have better performance at low temperatures.https://www.mdpi.com/2079-9292/12/15/3237Cryo-CMOSquantum computersphase-locked loopF-CLASS VCOpower filtertail resistor |
| spellingShingle | Kewei Xin Mingche Lai Fangxu Lv Kaile Guo Zhengbin Pang Chaolong Xu Geng Zhang Wenchen Wang Meng Li A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers Electronics Cryo-CMOS quantum computers phase-locked loop F-CLASS VCO power filter tail resistor |
| title | A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers |
| title_full | A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers |
| title_fullStr | A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers |
| title_full_unstemmed | A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers |
| title_short | A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers |
| title_sort | cryo cmos low power low noise phase locked loop design for quantum computers |
| topic | Cryo-CMOS quantum computers phase-locked loop F-CLASS VCO power filter tail resistor |
| url | https://www.mdpi.com/2079-9292/12/15/3237 |
| work_keys_str_mv | AT keweixin acryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT mingchelai acryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT fangxulv acryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT kaileguo acryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT zhengbinpang acryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT chaolongxu acryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT gengzhang acryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT wenchenwang acryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT mengli acryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT keweixin cryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT mingchelai cryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT fangxulv cryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT kaileguo cryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT zhengbinpang cryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT chaolongxu cryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT gengzhang cryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT wenchenwang cryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers AT mengli cryocmoslowpowerlownoisephaselockedloopdesignforquantumcomputers |