Design and Implementation of Asynchronous Processor on FPGA
Low-power and fault-tolerant features for microprocessors have been recognized as two of the greatest concerns in applications for edge devices. In this study, we propose asynchronous circuit design techniques for field-programmable gate arrays (FPGA) that can fundamentally overcome the drawbacks of...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2022-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9941072/ |
| _version_ | 1811312689566187520 |
|---|---|
| author | Ziho Shin Myeong-Hoon Oh |
| author_facet | Ziho Shin Myeong-Hoon Oh |
| author_sort | Ziho Shin |
| collection | DOAJ |
| description | Low-power and fault-tolerant features for microprocessors have been recognized as two of the greatest concerns in applications for edge devices. In this study, we propose asynchronous circuit design techniques for field-programmable gate arrays (FPGA) that can fundamentally overcome the drawbacks of conventional synchronous circuit designs. We used commercial FPGAs and implemented an asynchronous MSP430 microprocessor using the proposed technique. We also introduce an interfacing architecture between the synchronous block memory and asynchronous core to support the congeniality of the commercial embedded processor and the asynchronous core. Furthermore, we analyze a compiler for MSP430 and adapt its result to achieve a high-level development environment for asynchronous MSP430. The experimental results showed that the asynchronous MSP430 consumes 62.3% less power than its synchronous counterpart and has significant fault tolerance compared to the synchronous MSP430 under unstable supply voltage conditions. Additionally, the asynchronous MSP430 emitted 13% less electromagnetic noise at the working frequency. |
| first_indexed | 2024-04-13T10:41:17Z |
| format | Article |
| id | doaj.art-32837e62c540423b8a67248f5fbdb20e |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-13T10:41:17Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-32837e62c540423b8a67248f5fbdb20e2022-12-22T02:49:55ZengIEEEIEEE Access2169-35362022-01-011011837011837910.1109/ACCESS.2022.32206609941072Design and Implementation of Asynchronous Processor on FPGAZiho Shin0https://orcid.org/0000-0002-8644-2226Myeong-Hoon Oh1https://orcid.org/0000-0002-6019-1422The Affiliated Institute of Electronics and Telecommunication Research Institute (ETRI), Daejeon, Republic of KoreaDepartment of Computer Engineering, Honam University, Gwangju, Republic of KoreaLow-power and fault-tolerant features for microprocessors have been recognized as two of the greatest concerns in applications for edge devices. In this study, we propose asynchronous circuit design techniques for field-programmable gate arrays (FPGA) that can fundamentally overcome the drawbacks of conventional synchronous circuit designs. We used commercial FPGAs and implemented an asynchronous MSP430 microprocessor using the proposed technique. We also introduce an interfacing architecture between the synchronous block memory and asynchronous core to support the congeniality of the commercial embedded processor and the asynchronous core. Furthermore, we analyze a compiler for MSP430 and adapt its result to achieve a high-level development environment for asynchronous MSP430. The experimental results showed that the asynchronous MSP430 consumes 62.3% less power than its synchronous counterpart and has significant fault tolerance compared to the synchronous MSP430 under unstable supply voltage conditions. Additionally, the asynchronous MSP430 emitted 13% less electromagnetic noise at the working frequency.https://ieeexplore.ieee.org/document/9941072/Asynchronous circuitsfield-programmable gate arraysmicroprocessors |
| spellingShingle | Ziho Shin Myeong-Hoon Oh Design and Implementation of Asynchronous Processor on FPGA IEEE Access Asynchronous circuits field-programmable gate arrays microprocessors |
| title | Design and Implementation of Asynchronous Processor on FPGA |
| title_full | Design and Implementation of Asynchronous Processor on FPGA |
| title_fullStr | Design and Implementation of Asynchronous Processor on FPGA |
| title_full_unstemmed | Design and Implementation of Asynchronous Processor on FPGA |
| title_short | Design and Implementation of Asynchronous Processor on FPGA |
| title_sort | design and implementation of asynchronous processor on fpga |
| topic | Asynchronous circuits field-programmable gate arrays microprocessors |
| url | https://ieeexplore.ieee.org/document/9941072/ |
| work_keys_str_mv | AT zihoshin designandimplementationofasynchronousprocessoronfpga AT myeonghoonoh designandimplementationofasynchronousprocessoronfpga |