Architecture of the discrete sosine transformation processor for image compression systems on the losless-to-lossy circuit
The hardware implementations of fixed-point DCT blocks, known as IntDCT [1] and BinDCT [2], require some solutions. One of the main issues is the choice between the implementation of the conversion on FPGA, or the implementation on a digital signal processor (Digital Signal Processor, DSP). Each of...
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| Format: | Article |
| Language: | Russian |
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Educational institution «Belarusian State University of Informatics and Radioelectronics»
2021-08-01
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| Series: | Doklady Belorusskogo gosudarstvennogo universiteta informatiki i radioèlektroniki |
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| Online Access: | https://doklady.bsuir.by/jour/article/view/3141 |