Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA
In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to...
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IEEE
2021-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9380138/ |
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| author | P. Veda Bhanu Rahul Govindan Plava Kattamuri J. Soumya Linga Reddy Cenkeramaddi |
| author_facet | P. Veda Bhanu Rahul Govindan Plava Kattamuri J. Soumya Linga Reddy Cenkeramaddi |
| author_sort | P. Veda Bhanu |
| collection | DOAJ |
| description | In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper presents the flexible placement of spare core onto Torus topology-based NoC design by considering core faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing algorithm, run-time fault injection model, and fault-tolerant placement of spare core onto Torus topology using an FPGA. Experiments have been done by taking different multimedia and synthetic application benchmarks. This has been done in both static and dynamic simulation environments followed by hardware implementation. In the static simulation environment, the experimentations are carried out by scaling the network size and router faults in the network. The results obtained from our approach outperform the methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size, our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of the proposed approach over the approaches presented in the literature. |
| first_indexed | 2024-12-13T18:44:36Z |
| format | Article |
| id | doaj.art-331b8a5e891a4d9b922d5c287fe47a3d |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-13T18:44:36Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
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| spelling | doaj.art-331b8a5e891a4d9b922d5c287fe47a3d2022-12-21T23:35:06ZengIEEEIEEE Access2169-35362021-01-019459354595410.1109/ACCESS.2021.30665379380138Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGAP. Veda Bhanu0https://orcid.org/0000-0001-5663-8407Rahul Govindan1https://orcid.org/0000-0002-9581-0705Plava Kattamuri2J. Soumya3Linga Reddy Cenkeramaddi4https://orcid.org/0000-0002-1023-2118Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani-Hyderabad Campus, Hyderabad, IndiaDepartment of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani-Hyderabad Campus, Hyderabad, IndiaDepartment of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani-Hyderabad Campus, Hyderabad, IndiaDepartment of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani-Hyderabad Campus, Hyderabad, IndiaDepartment of Information and Communication Technology, University of Agder (UiA), Grimstad, NorwayIn the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper presents the flexible placement of spare core onto Torus topology-based NoC design by considering core faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing algorithm, run-time fault injection model, and fault-tolerant placement of spare core onto Torus topology using an FPGA. Experiments have been done by taking different multimedia and synthetic application benchmarks. This has been done in both static and dynamic simulation environments followed by hardware implementation. In the static simulation environment, the experimentations are carried out by scaling the network size and router faults in the network. The results obtained from our approach outperform the methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size, our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of the proposed approach over the approaches presented in the literature.https://ieeexplore.ieee.org/document/9380138/Network-on-chipapplication mappingtorus topologyfault-tolerancespare corecommunication cost |
| spellingShingle | P. Veda Bhanu Rahul Govindan Plava Kattamuri J. Soumya Linga Reddy Cenkeramaddi Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA IEEE Access Network-on-chip application mapping torus topology fault-tolerance spare core communication cost |
| title | Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA |
| title_full | Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA |
| title_fullStr | Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA |
| title_full_unstemmed | Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA |
| title_short | Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA |
| title_sort | flexible spare core placement in torus topology based nocs and its validation on an fpga |
| topic | Network-on-chip application mapping torus topology fault-tolerance spare core communication cost |
| url | https://ieeexplore.ieee.org/document/9380138/ |
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