Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP
Unconventional functions, including activation functions and power functions, are extremely hard-to-realize primarily due to the difficulty in arriving at the hierarchical design. The hierarchical design allows the synthesis tool to map the functionality with that of standard cells employed through...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Hindawi-IET
2024-01-01
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| Series: | IET Computers & Digital Techniques |
| Online Access: | http://dx.doi.org/10.1049/2024/6623637 |
| _version_ | 1797323898659799040 |
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| author | H. C. Prashanth Madhav Rao |
| author_facet | H. C. Prashanth Madhav Rao |
| author_sort | H. C. Prashanth |
| collection | DOAJ |
| description | Unconventional functions, including activation functions and power functions, are extremely hard-to-realize primarily due to the difficulty in arriving at the hierarchical design. The hierarchical design allows the synthesis tool to map the functionality with that of standard cells employed through the regular ASIC synthesis flow. For conventional functions, the hierarchical design is structured and then supplied to the synthesis flow, whereas, for unconventional functions, the same method is not reliable, since the current synthesis method does not offer any design-space exploration scheme to arrive at an easy-to-realize design entity. The unconventional functions either take a long synthesis run-time or additional efforts are spent in restructuring the hierarchical design for the desired function to synthesizable ones. Cartesian genetic programing (CGP) allows to not only incorporate custom logic gates for synthesizing the hierarchical design but also aids in the design-space exploration for the targeted function through the custom gates. The CGP configuration evolves difficult-to-realize complex functions with multiple solutions, and filtering through desired Pareto-optimal requirements offers a unique hierarchical design. Incorporating CGP-derived hierarchical designs into the traditional synthesis flow is instrumental for implementing and evaluating higher-order designs comprising nonlinear functional constructs. Six activation functions and power functions that fall in the category of unconventional functions are realized by the CGP method using custom cells to demonstrate the capability. Further, the hierarchical design of these unconventional functions is flattened and compared with the same function that is directly synthesized using basic gates. The CGP-derived synthesis method reports 3× less synthesis time for realizing the complex functions at the hierarchical level compared to the synthesis using basic gate cells. Hardware characteristics and error metrics are also investigated for the CGP realized complex functions and are made freely available for further usage to the research and designers’ community. |
| first_indexed | 2024-03-08T05:35:41Z |
| format | Article |
| id | doaj.art-3384702895284a64976bfe258ee39e6e |
| institution | Directory Open Access Journal |
| issn | 1751-861X |
| language | English |
| last_indexed | 2024-03-08T05:35:41Z |
| publishDate | 2024-01-01 |
| publisher | Hindawi-IET |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj.art-3384702895284a64976bfe258ee39e6e2024-02-06T00:00:24ZengHindawi-IETIET Computers & Digital Techniques1751-861X2024-01-01202410.1049/2024/6623637Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGPH. C. Prashanth0Madhav Rao1International Institute of Information Technology BangaloreInternational Institute of Information Technology BangaloreUnconventional functions, including activation functions and power functions, are extremely hard-to-realize primarily due to the difficulty in arriving at the hierarchical design. The hierarchical design allows the synthesis tool to map the functionality with that of standard cells employed through the regular ASIC synthesis flow. For conventional functions, the hierarchical design is structured and then supplied to the synthesis flow, whereas, for unconventional functions, the same method is not reliable, since the current synthesis method does not offer any design-space exploration scheme to arrive at an easy-to-realize design entity. The unconventional functions either take a long synthesis run-time or additional efforts are spent in restructuring the hierarchical design for the desired function to synthesizable ones. Cartesian genetic programing (CGP) allows to not only incorporate custom logic gates for synthesizing the hierarchical design but also aids in the design-space exploration for the targeted function through the custom gates. The CGP configuration evolves difficult-to-realize complex functions with multiple solutions, and filtering through desired Pareto-optimal requirements offers a unique hierarchical design. Incorporating CGP-derived hierarchical designs into the traditional synthesis flow is instrumental for implementing and evaluating higher-order designs comprising nonlinear functional constructs. Six activation functions and power functions that fall in the category of unconventional functions are realized by the CGP method using custom cells to demonstrate the capability. Further, the hierarchical design of these unconventional functions is flattened and compared with the same function that is directly synthesized using basic gates. The CGP-derived synthesis method reports 3× less synthesis time for realizing the complex functions at the hierarchical level compared to the synthesis using basic gate cells. Hardware characteristics and error metrics are also investigated for the CGP realized complex functions and are made freely available for further usage to the research and designers’ community.http://dx.doi.org/10.1049/2024/6623637 |
| spellingShingle | H. C. Prashanth Madhav Rao Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP IET Computers & Digital Techniques |
| title | Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP |
| title_full | Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP |
| title_fullStr | Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP |
| title_full_unstemmed | Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP |
| title_short | Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP |
| title_sort | accelerated and highly correlated asic synthesis of ai hardware subsystems using cgp |
| url | http://dx.doi.org/10.1049/2024/6623637 |
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