A Second-Order Single Loop Oversampling Analog-to-Digital Converter (ADC) with Proposed Hybrid Feedforward/Feedback Architecture
This paper proposes hybrid architecture of feedforward/feedback second order single-loop modulator for high resolution analog-to-digital converter (ADC) applications. Different techniques for oversampling modulator are discussed. The proposed architecture consists of three stages. The first stage is...
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| Format: | Article |
| Language: | English |
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Unviversity of Technology- Iraq
2012-07-01
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| Series: | Engineering and Technology Journal |
| Subjects: | |
| Online Access: | https://etj.uotechnology.edu.iq/article_60859_fc4d03bafe08244b5ff9ce2ba59b1d64.pdf |
| _version_ | 1797325496263901184 |
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| author | Hasan M. Azzawi |
| author_facet | Hasan M. Azzawi |
| author_sort | Hasan M. Azzawi |
| collection | DOAJ |
| description | This paper proposes hybrid architecture of feedforward/feedback second order single-loop modulator for high resolution analog-to-digital converter (ADC) applications. Different techniques for oversampling modulator are discussed. The proposed architecture consists of three stages. The first stage is 2nd order single loop oversampling ADC with novel feedforward/feedback architecture. In the second stage, an error cancellation circuit (ECC) is proposed at the output of the modulator to noise shaping of quantization noise. In addition, the third stage is a decimation filter in order to reduce the oversampling ratio (OSR) which is suitable for broadband applications. With low OSR=24, the signal-to-noise ratio (SNR) is improved about 55 dB if compared with traditional architecture (feedback singleloop high order topology). The achieved resolution or the effective number of bits (ENOB) is (22-bit). With high OSR=256, the net improvement in quantization noise reduction is 64 dB if compared with feedforward architecture (single-loop high order) and the ENOB=28. Finally a 1-bit quantizer is used in the proposed architecture which greatly decreases the circuit implementation complexity and power consumption. Simulation results show the superiority performance of proposed hybrid architecture as compared with traditional modulator topologies (feedforward and feedback). |
| first_indexed | 2024-03-08T06:10:16Z |
| format | Article |
| id | doaj.art-33f7b0b47007402fa91634abcd8a2302 |
| institution | Directory Open Access Journal |
| issn | 1681-6900 2412-0758 |
| language | English |
| last_indexed | 2024-03-08T06:10:16Z |
| publishDate | 2012-07-01 |
| publisher | Unviversity of Technology- Iraq |
| record_format | Article |
| series | Engineering and Technology Journal |
| spelling | doaj.art-33f7b0b47007402fa91634abcd8a23022024-02-04T17:39:46ZengUnviversity of Technology- IraqEngineering and Technology Journal1681-69002412-07582012-07-0130132209222810.30684/etj.30.13.560859A Second-Order Single Loop Oversampling Analog-to-Digital Converter (ADC) with Proposed Hybrid Feedforward/Feedback ArchitectureHasan M. AzzawiThis paper proposes hybrid architecture of feedforward/feedback second order single-loop modulator for high resolution analog-to-digital converter (ADC) applications. Different techniques for oversampling modulator are discussed. The proposed architecture consists of three stages. The first stage is 2nd order single loop oversampling ADC with novel feedforward/feedback architecture. In the second stage, an error cancellation circuit (ECC) is proposed at the output of the modulator to noise shaping of quantization noise. In addition, the third stage is a decimation filter in order to reduce the oversampling ratio (OSR) which is suitable for broadband applications. With low OSR=24, the signal-to-noise ratio (SNR) is improved about 55 dB if compared with traditional architecture (feedback singleloop high order topology). The achieved resolution or the effective number of bits (ENOB) is (22-bit). With high OSR=256, the net improvement in quantization noise reduction is 64 dB if compared with feedforward architecture (single-loop high order) and the ENOB=28. Finally a 1-bit quantizer is used in the proposed architecture which greatly decreases the circuit implementation complexity and power consumption. Simulation results show the superiority performance of proposed hybrid architecture as compared with traditional modulator topologies (feedforward and feedback).https://etj.uotechnology.edu.iq/article_60859_fc4d03bafe08244b5ff9ce2ba59b1d64.pdfadcfeedforwardfeedbacksingleloop high order converter |
| spellingShingle | Hasan M. Azzawi A Second-Order Single Loop Oversampling Analog-to-Digital Converter (ADC) with Proposed Hybrid Feedforward/Feedback Architecture Engineering and Technology Journal adc feedforward feedback single loop high order converter |
| title | A Second-Order Single Loop Oversampling Analog-to-Digital Converter (ADC) with Proposed Hybrid Feedforward/Feedback Architecture |
| title_full | A Second-Order Single Loop Oversampling Analog-to-Digital Converter (ADC) with Proposed Hybrid Feedforward/Feedback Architecture |
| title_fullStr | A Second-Order Single Loop Oversampling Analog-to-Digital Converter (ADC) with Proposed Hybrid Feedforward/Feedback Architecture |
| title_full_unstemmed | A Second-Order Single Loop Oversampling Analog-to-Digital Converter (ADC) with Proposed Hybrid Feedforward/Feedback Architecture |
| title_short | A Second-Order Single Loop Oversampling Analog-to-Digital Converter (ADC) with Proposed Hybrid Feedforward/Feedback Architecture |
| title_sort | second order single loop oversampling analog to digital converter adc with proposed hybrid feedforward feedback architecture |
| topic | adc feedforward feedback single loop high order converter |
| url | https://etj.uotechnology.edu.iq/article_60859_fc4d03bafe08244b5ff9ce2ba59b1d64.pdf |
| work_keys_str_mv | AT hasanmazzawi asecondordersingleloopoversamplinganalogtodigitalconverteradcwithproposedhybridfeedforwardfeedbackarchitecture AT hasanmazzawi secondordersingleloopoversamplinganalogtodigitalconverteradcwithproposedhybridfeedforwardfeedbackarchitecture |