Hardware Implementation of Artificial Neural Network for Data Ciphering
This paper introduces the design and realization of multiple blocks ciphering techniques on the FPGA (Field Programmable Gate Arrays). A back propagation neural networks have been built for substitution, permutation and XOR blocks ciphering using Neural Network Toolbox in MATLAB program. They are tr...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Tikrit University
2016-05-01
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| Series: | Tikrit Journal of Engineering Sciences |
| Subjects: | |
| Online Access: | https://tj-es.com/ojs/index.php/tjes/article/view/289 |
| _version_ | 1797782469808750592 |
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| author | Sahar L. Kadoory Toka A. Fatehi Qutaiba A. Hasan |
| author_facet | Sahar L. Kadoory Toka A. Fatehi Qutaiba A. Hasan |
| author_sort | Sahar L. Kadoory |
| collection | DOAJ |
| description | This paper introduces the design and realization of multiple blocks ciphering techniques on the FPGA (Field Programmable Gate Arrays). A back propagation neural networks have been built for substitution, permutation and XOR blocks ciphering using Neural Network Toolbox in MATLAB program. They are trained to encrypt the data, after obtaining the suitable weights, biases, activation function and layout. Afterward, they are described using VHDL and implemented using Xilinx Spartan-3E FPGA using two approaches: serial and parallel versions. The simulation results obtained with Xilinx ISE 9.2i software. The numerical precision is chosen carefully when implementing the Neural Network on FPGA. Obtained results from the hardware designs show accurate numeric values to cipher the data. As expected, the synthesis results indicate that the serial version requires less area resources than the parallel version. As, the data throughput in parallel version is higher than the serial version in rang between (1.13-1.5) times. Also, a slight difference can be observed in the maximum frequency.
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| first_indexed | 2024-03-13T00:11:24Z |
| format | Article |
| id | doaj.art-345576f7bfd5459ba306226cfd5527c0 |
| institution | Directory Open Access Journal |
| issn | 1813-162X 2312-7589 |
| language | English |
| last_indexed | 2024-03-13T00:11:24Z |
| publishDate | 2016-05-01 |
| publisher | Tikrit University |
| record_format | Article |
| series | Tikrit Journal of Engineering Sciences |
| spelling | doaj.art-345576f7bfd5459ba306226cfd5527c02023-07-12T12:54:02ZengTikrit UniversityTikrit Journal of Engineering Sciences1813-162X2312-75892016-05-0123210.25130/tjes.23.2.09Hardware Implementation of Artificial Neural Network for Data CipheringSahar L. Kadoory0Toka A. Fatehi1Qutaiba A. Hasan2Electronics Engineering College, University of Mosul, Mosul, IraqElectronics Engineering College, University of Mosul, Mosul, IraqPetroleum and Minerals Engineering College, Tikrit University, Salahaldeen, IraqThis paper introduces the design and realization of multiple blocks ciphering techniques on the FPGA (Field Programmable Gate Arrays). A back propagation neural networks have been built for substitution, permutation and XOR blocks ciphering using Neural Network Toolbox in MATLAB program. They are trained to encrypt the data, after obtaining the suitable weights, biases, activation function and layout. Afterward, they are described using VHDL and implemented using Xilinx Spartan-3E FPGA using two approaches: serial and parallel versions. The simulation results obtained with Xilinx ISE 9.2i software. The numerical precision is chosen carefully when implementing the Neural Network on FPGA. Obtained results from the hardware designs show accurate numeric values to cipher the data. As expected, the synthesis results indicate that the serial version requires less area resources than the parallel version. As, the data throughput in parallel version is higher than the serial version in rang between (1.13-1.5) times. Also, a slight difference can be observed in the maximum frequency. https://tj-es.com/ojs/index.php/tjes/article/view/289Back propagationCipheringEncryptionFPGANeural NetworkVHDL |
| spellingShingle | Sahar L. Kadoory Toka A. Fatehi Qutaiba A. Hasan Hardware Implementation of Artificial Neural Network for Data Ciphering Tikrit Journal of Engineering Sciences Back propagation Ciphering Encryption FPGA Neural Network VHDL |
| title | Hardware Implementation of Artificial Neural Network for Data Ciphering |
| title_full | Hardware Implementation of Artificial Neural Network for Data Ciphering |
| title_fullStr | Hardware Implementation of Artificial Neural Network for Data Ciphering |
| title_full_unstemmed | Hardware Implementation of Artificial Neural Network for Data Ciphering |
| title_short | Hardware Implementation of Artificial Neural Network for Data Ciphering |
| title_sort | hardware implementation of artificial neural network for data ciphering |
| topic | Back propagation Ciphering Encryption FPGA Neural Network VHDL |
| url | https://tj-es.com/ojs/index.php/tjes/article/view/289 |
| work_keys_str_mv | AT saharlkadoory hardwareimplementationofartificialneuralnetworkfordataciphering AT tokaafatehi hardwareimplementationofartificialneuralnetworkfordataciphering AT qutaibaahasan hardwareimplementationofartificialneuralnetworkfordataciphering |