Line‐transient enhancement techniques for multi‐path hybrid DC–DC converter with <1% output overshoot/undershoot
Abstract This letter presents two transient enhancement techniques for multi‐path switched‐capacitor‐inductor (MP‐SCI) hybrid DC–DC converters to eliminate the line‐transient‐induced voltage coupling to the converter output. Since the existing input‐feedforward method is hard to apply to the MP‐SCI...
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Wiley
2022-12-01
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Series: | Electronics Letters |
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Online Access: | https://doi.org/10.1049/ell2.12634 |
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author | Huihua Li Qiaobo Ma Yang Jiang Man‐Kay Law Pui‐In Mak Rui P. Martins |
author_facet | Huihua Li Qiaobo Ma Yang Jiang Man‐Kay Law Pui‐In Mak Rui P. Martins |
author_sort | Huihua Li |
collection | DOAJ |
description | Abstract This letter presents two transient enhancement techniques for multi‐path switched‐capacitor‐inductor (MP‐SCI) hybrid DC–DC converters to eliminate the line‐transient‐induced voltage coupling to the converter output. Since the existing input‐feedforward method is hard to apply to the MP‐SCI converter, the proposed techniques tackle the intrinsic hard‐charging property with the MP‐SCI topology, preventing the line‐coupling current through topology operation reconfiguration and power‐switch modulation. The proposed controller also achieves adaptive line‐transition detection and automatic flying‐capacitor voltage balancing, ensuring a fast line regulation feature. Implemented with an MP‐SCI topology for a 9 to 14 V‐input to 5 V‐output conversion, the proposed control techniques provide an output (VOUT) overshoot and undershoot as low as 0.5% of the output DC level under a 3‐V input voltage step. From the simulation, the corresponding output variation reduction can be more than 94% when compared with the existing MP‐SCI operations. Besides, the proposed controller is compatible with a voltage‐mode (VM) V2 pulse‐width modulation (PWM) function, achieving a fast load‐transient recovery in six switching cycles and a VOUT variation of 75 mV at a 5 V DC level under a 0‐to‐3 A load step. The peak conversion efficiency can be as high as 95.5%, and the targeted load current delivery is up to 3 A. |
first_indexed | 2024-04-11T14:03:25Z |
format | Article |
id | doaj.art-3493790e306b450286e5f18008f729c4 |
institution | Directory Open Access Journal |
issn | 0013-5194 1350-911X |
language | English |
last_indexed | 2024-04-11T14:03:25Z |
publishDate | 2022-12-01 |
publisher | Wiley |
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series | Electronics Letters |
spelling | doaj.art-3493790e306b450286e5f18008f729c42022-12-22T04:20:00ZengWileyElectronics Letters0013-51941350-911X2022-12-01582595295610.1049/ell2.12634Line‐transient enhancement techniques for multi‐path hybrid DC–DC converter with <1% output overshoot/undershootHuihua Li0Qiaobo Ma1Yang Jiang2Man‐Kay Law3Pui‐In Mak4Rui P. Martins5State Key Laboratory of Analog and Mixed‐Signal VLSI, IME, and FST‐ECE University of Macau Macau ChinaState Key Laboratory of Analog and Mixed‐Signal VLSI, IME, and FST‐ECE University of Macau Macau ChinaState Key Laboratory of Analog and Mixed‐Signal VLSI, IME, and FST‐ECE University of Macau Macau ChinaState Key Laboratory of Analog and Mixed‐Signal VLSI, IME, and FST‐ECE University of Macau Macau ChinaState Key Laboratory of Analog and Mixed‐Signal VLSI, IME, and FST‐ECE University of Macau Macau ChinaState Key Laboratory of Analog and Mixed‐Signal VLSI, IME, and FST‐ECE University of Macau Macau ChinaAbstract This letter presents two transient enhancement techniques for multi‐path switched‐capacitor‐inductor (MP‐SCI) hybrid DC–DC converters to eliminate the line‐transient‐induced voltage coupling to the converter output. Since the existing input‐feedforward method is hard to apply to the MP‐SCI converter, the proposed techniques tackle the intrinsic hard‐charging property with the MP‐SCI topology, preventing the line‐coupling current through topology operation reconfiguration and power‐switch modulation. The proposed controller also achieves adaptive line‐transition detection and automatic flying‐capacitor voltage balancing, ensuring a fast line regulation feature. Implemented with an MP‐SCI topology for a 9 to 14 V‐input to 5 V‐output conversion, the proposed control techniques provide an output (VOUT) overshoot and undershoot as low as 0.5% of the output DC level under a 3‐V input voltage step. From the simulation, the corresponding output variation reduction can be more than 94% when compared with the existing MP‐SCI operations. Besides, the proposed controller is compatible with a voltage‐mode (VM) V2 pulse‐width modulation (PWM) function, achieving a fast load‐transient recovery in six switching cycles and a VOUT variation of 75 mV at a 5 V DC level under a 0‐to‐3 A load step. The peak conversion efficiency can be as high as 95.5%, and the targeted load current delivery is up to 3 A.https://doi.org/10.1049/ell2.12634DC–DC power convertorsintegrated circuit designmixed analogue digital integrated circuits |
spellingShingle | Huihua Li Qiaobo Ma Yang Jiang Man‐Kay Law Pui‐In Mak Rui P. Martins Line‐transient enhancement techniques for multi‐path hybrid DC–DC converter with <1% output overshoot/undershoot Electronics Letters DC–DC power convertors integrated circuit design mixed analogue digital integrated circuits |
title | Line‐transient enhancement techniques for multi‐path hybrid DC–DC converter with <1% output overshoot/undershoot |
title_full | Line‐transient enhancement techniques for multi‐path hybrid DC–DC converter with <1% output overshoot/undershoot |
title_fullStr | Line‐transient enhancement techniques for multi‐path hybrid DC–DC converter with <1% output overshoot/undershoot |
title_full_unstemmed | Line‐transient enhancement techniques for multi‐path hybrid DC–DC converter with <1% output overshoot/undershoot |
title_short | Line‐transient enhancement techniques for multi‐path hybrid DC–DC converter with <1% output overshoot/undershoot |
title_sort | line transient enhancement techniques for multi path hybrid dc dc converter with 1 output overshoot undershoot |
topic | DC–DC power convertors integrated circuit design mixed analogue digital integrated circuits |
url | https://doi.org/10.1049/ell2.12634 |
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